AD9251BCPZ-40 Analog Devices Inc, AD9251BCPZ-40 Datasheet - Page 32

• Manufacturer Part Number: AD9251BCPZ-40
• Description: 14 BIT DUAL 40 Msps Low Power ADC
• Manufacturer: Analog Devices Inc

Specifications of AD9251BCPZ-40

• Number Of Bits: 14
• Sampling Rate (per Second): 40M
• Data Interface: Serial, SPI™
• Number Of Converters: 2
• Power Dissipation (max): 105.5mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9251
MEMORY MAP REGISTER TABLE
All address and bit locations that are not included in Table 16 are not currently supported for this device.
Table 16.
Address
(Hex)
Chip Configuration Registers
0x00
0x01
0x02
Device Index and Transfer Registers
0x05
0xFF
Program Registers (May or May Not Be Indexed by Device Index)
0x08
0x09
0x0B
Register
Name
SPI port
configuration
(global)
Chip ID (global)
Chip grade
(global)
Channel index
Transfer
Modes
Clock (global)
Clock divide
(global)
Bit 7
(MSB)
0
8-bit chip ID bits [7:0]
AD9251 = 0x23
Open
Open
Open
External
power-
down
enable
(local)
Open
Open
Bit 6
LSB
first
Speed grade ID 6:4
20 MSPS = 000
40 MSPS = 001
65 MSPS = 010
80 MSPS = 011
Open
Open
External pin function
0x00 full power-
down
0x01 standby
(local)
Open
Bit 5
Soft reset
Open
Open
Open
Rev. A | Page 32 of 36
Bit 4
1
Open
Open
Open
Open
Bit 3
1
Open
Open
Open
Open
Bit 2
Soft
reset
Open
Open
Clock divider [2:0]
Clock divide ratio
000 = divide by 1
001 = divide by 2
010 = divide by 3
011 = divide by 4
100 = divide by 5
101 = divide by 6
110 = divide by 7
111 = divide by 8
Bit 1
LSB first
ADC B
default
Open
00 = chip run
01 = full power-
down
10 = standby
11 = chip wide
digital reset
(local)
Open
Bit 0
(LSB)
0
ADC A
default
Transfer
Duty
cycle
stabilize
Default
Value
(Hex)
0x18
0x03
0x00
0x80
0x00
0x00
Comments
The nibbles are
mirrored so
that LSB- or
MSB-first mode
registers
correctly,
regardless of
shift mode
Unique chip ID
used to diffe-
rentiate
devices; read
only
Unique speed
grade ID used
to differentiate
devices; read
only
Bits are set to
determine
which device
on chip
receives the
next write
command; the
default is all
devices on chip
Synchronously
transfers data
from the
master shift
register to the
slave
Determines
various generic
modes of chip
operation
The divide ratio
is the value
plus 1