AD9266BCPZ-80 Analog Devices Inc, AD9266BCPZ-80 Datasheet
AD9266BCPZ-80
Specifications of AD9266BCPZ-80
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AD9266BCPZ-80 Summary of contents
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FEATURES 1.8 V analog supply operation 1 3.3 V output supply SNR 77.6 dBFS at 9.7 MHz input 71.1 dBFS at 200 MHz input SFDR 93 dBc at 9.7 MHz input 80 dBc at 200 MHz input Low ...
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AD9266 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 Functional Block Diagram .............................................................. 1 Product Highlights ........................................................................... 1 Revision History ............................................................................... 2 General Description ......................................................................... 3 Specifications ..................................................................................... 4 DC Specifications ......................................................................... 4 AC Specifications .......................................................................... 5 Digital Specifications ...
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GENERAL DESCRIPTION The AD9266 is a monolithic, single-channel 1.8 V supply, 16-bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS analog-to-digital converter (ADC). It features a high performance sample-and- hold circuit and on-chip voltage reference. The product uses multistage differential pipeline architecture with ...
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AD9266 SPECIFICATIONS DC SPECIFICATIONS AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty cycle clock, DCS disabled, unless otherwise noted. Table 1. Parameter ...
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AC SPECIFICATIONS AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty cycle clock, DCS disabled, unless otherwise noted. Table 2. 1 Parameter SIGNAL-TO-NOISE ...
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AD9266 DIGITAL SPECIFICATIONS AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty cycle clock, DCS disabled, unless otherwise noted. Table 3. Parameter DIFFERENTIAL ...
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SWITCHING SPECIFICATIONS AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty cycle clock, DCS disabled, unless otherwise noted. Table 4. Parameter CLOCK INPUT ...
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AD9266 TIMING SPECIFICATIONS Table 5. Parameter Conditions SPI TIMING REQUIREMENTS t Setup time between the data and the rising edge of SCLK DS t Hold time between the data and the rising edge of SCLK DH t Period of the ...
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ABSOLUTE MAXIMUM RATINGS Table 6. Parameter AVDD to AGND DRVDD to AGND VIN+, VIN− to AGND CLK+, CLK− to AGND VREF to AGND SENSE to AGND VCM to AGND RBIAS to AGND CSB to AGND SCLK/DFS to AGND SDIO/PDWN to ...
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AD9266 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Table 8. Pin Function Descriptions Pin No. Mnemonic Description 0, Exposed Paddle AGND The exposed paddle is the only ground connection on the chip. It must be soldered to the analog ground of the ...
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TYPICAL PERFORMANCE CHARACTERISTICS AD9266-80 AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty cycle clock, DCS disabled, unless otherwise noted. 0 80MSPS 9.7MHz ...
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AD9266 AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty cycle clock, DCS disabled, unless otherwise noted. 100 SFDR (dBc ...
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AD9266-65 AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty cycle clock, DCS disabled, unless otherwise noted. 0 65MSPS 9.7MHz @ –1dBFS –20 ...
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AD9266 AD9266-40 AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty cycle clock, DCS disabled, unless otherwise noted. 0 40MSPS 9.7MHz @ –1dBFS ...
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AD9266-20 AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty cycle clock, DCS disabled, unless otherwise noted. 0 20MSPS 9.7MHz @ –1dBFS –20 ...
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AD9266 EQUIVALENT CIRCUITS AVDD VIN± Figure 27. Equivalent Analog Input Circuit AVDD VREF 7.5kΩ Figure 28. Equivalent VREF Circuit AVDD 375Ω SENSE Figure 29. Equivalent SENSE Circuit AVDD 5Ω CLK+ 15kΩ AVDD 15kΩ 5Ω CLK– Figure 30. Equivalent Clock Input ...
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THEORY OF OPERATION The AD9266 architecture consists of a multistage, pipelined ADC. Each stage provides sufficient overlap to correct for flash errors in the preceding stage. The quantized outputs from each stage are combined into a final 16-bit result in ...
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AD9266 For baseband applications below ~10 MHz where SNR is a key parameter, differential transformer coupling is the recommended input configuration. An example is shown in Figure 38. To bias the analog input, the VCM voltage can be connected to ...
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VOLTAGE REFERENCE A stable and accurate 1.0 V voltage reference is built into the AD9266. The VREF can be configured using either the internal 1.0 V reference or an externally applied 1.0 V reference voltage. The various reference modes are ...
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AD9266 CLOCK INPUT CONSIDERATIONS For optimum performance, clock the AD9266 sample clock inputs, CLK+ and CLK−, with a differential signal. The signal is typically ac-coupled into the CLK+ and CLK− pins via a transformer or capacitors. These pins are biased ...
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Input Clock Divider The AD9266 contains an input clock divider with the ability to divide the input clock by integer values between 1 and 8. Optimum performance can be obtained by enabling the internal duty cycle stabilizer (DCS) when using ...
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AD9266 POWER DISSIPATION AND STANDBY MODE As shown in Figure 53, the analog core power dissipated by the AD9266 is proportional to its sample rate. The digital power dissipation of the CMOS outputs are determined primarily by the strength of ...
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TIMING The AD9266 provides latched data with a pipeline delay of eight clock cycles. Data outputs are available one propagation delay (t ) after the rising edge of the clock signal. PD Minimize the length of the output data lines ...
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AD9266 BUILT-IN SELF-TEST (BIST) AND OUTPUT TEST The AD9266 includes a built-in test feature that is designed to enable verification of the integrity of the datapath, as well as to facilitate board-level debugging. A built-in self-test (BIST) feature that verifies ...
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SERIAL PORT INTERFACE (SPI) The AD9266 serial port interface (SPI) allows the user to con- figure the converter for specific functions or operations through a structured register space provided inside the ADC. The SPI gives the user added flexibility and ...
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AD9266 HARDWARE INTERFACE The pins described in Table 13 constitute the physical interface between the programming device of the user and the serial port of the AD9266. The SCLK pin and the CSB pin function as inputs when using the ...
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MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Each row in the memory map register table (see Table 16) contains eight bit locations. The memory map is roughly divided into four sections: the chip configuration registers (Address 0x00 to Address ...
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AD9266 MEMORY MAP REGISTER TABLE All address and bit locations that are not included in Table 16 are not currently supported for this device. Table 16. Addr Bit 7 (Hex) Register Name (MSB) Bit 6 Chip Configuration Registers 0x00 SPI ...
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Addr Bit 7 Register Name Bit 6 (Hex) (MSB) 0x14 Output mode 00 = 3.3 V CMOS 10 = 1.8 V CMOS 0x15 Output adjust 3.3 V DCO drive strength stripe (default stripes 10 ...
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AD9266 MEMORY MAP REGISTER DESCRIPTIONS For additional information about functions that are controlled in Register 0x00 to Register 0xFF, see the AN-877 Application Note, Interfacing to High Speed ADCs via SPI at www.analog.com. USR2 (Register 0x101) Bit 3—Enable GCLK Detect ...
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APPLICATIONS INFORMATION DESIGN GUIDELINES Before starting design and layout of the AD9266 as a system recommended that the designer become familiar with these guidelines, which discuss the special circuit connections and layout requirements needed for certain pins. Power ...
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... PIN 1 INDICATOR 0.80 0.75 0.70 SEATING PLANE ORDERING GUIDE 1 Model Temperature Range AD9266BCPZ-80 –40°C to +85°C AD9266BCPZRL7-80 –40°C to +85°C AD9266BCPZ-65 –40°C to +85°C AD9266BCPZRL7-65 –40°C to +85°C AD9266BCPZ-40 –40°C to +85°C AD9266BCPZRL7-40 –40°C to +85°C AD9266BCPZ-20 – ...