AD9269BCPZRL7-65 Analog Devices Inc, AD9269BCPZRL7-65 Datasheet - Page 3

• Manufacturer Part Number: AD9269BCPZRL7-65
• Description: 16 Bit 65 Msps Low Pwr Dual ADC
• Manufacturer: Analog Devices Inc

Specifications of AD9269BCPZRL7-65

• Number Of Bits: 16
• Sampling Rate (per Second): 65M
• Data Interface: Serial, SPI™
• Number Of Converters: 2
• Power Dissipation (max): 199.8mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

GENERAL DESCRIPTION
The AD9269 is a monolithic, dual-channel, 1.8 V supply, 16-bit,
20/40/65/80 MSPS analog-to-digital converter (ADC). It features
a high performance sample-and-hold circuit and on-chip voltage
reference.
The product uses multistage differential pipeline architecture with
output error correction logic to provide 16-bit accuracy at 80 MSPS
data rates and to guarantee no missing codes over the full operating
temperature range.
The AD9269 incorporates an optional integrated dc correction and
quadrature error correction block (QEC) that corrects for dc
offset, gain, and phase mismatch between the two channels.
This functional block can be very beneficial to complex signal
processing applications such as direct conversion receivers.
The ADC also contains several features designed to maximize
flexibility and minimize system cost, such as programmable
clock and data alignment and programmable digital test pattern
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generation. The available digital test patterns include built-in
deterministic and pseudorandom patterns, along with custom
user-defined test patterns entered via the serial port interface (SPI).
A differential clock input controls all internal conversion cycles.
An optional duty cycle stabilizer (DCS) compensates for wide
variations in the clock duty cycle while maintaining excellent
overall ADC performance.
The digital output data is presented in offset binary, gray code,
or twos complement format. A data output clock (DCO) is pro-
vided for each ADC channel to ensure proper latch timing with
receiving logic. Both 1.8 V and 3.3 V CMOS levels are supported,
and output data can be multiplexed onto a single output bus.
The AD9269 is available in a 64-lead RoHS-compliant LFCSP
and is specified over the industrial temperature range (−40°C to
+85°C).
AD9269