AD9273BSVZ-50 Analog Devices Inc, AD9273BSVZ-50 Datasheet - Page 32

• Manufacturer Part Number: AD9273BSVZ-50
• Description: 12Bit 50 MSPS Octal ADC
• Manufacturer: Analog Devices Inc
• Type: Crosspoint Switchr

Specifications of AD9273BSVZ-50

• Resolution (bits): 12 b
• Sampling Rate (per Second): 50M
• Data Interface: Serial
• Voltage Supply Source: Single Supply
• Voltage - Supply: 1.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP Exposed Pad, 100-eTQFP, 100-HTQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9273
The duty cycle stabilizer uses a delay-locked loop (DLL) to
create the nonsampling edge. As a result, any changes to the
sampling frequency require approximately eight clock cycles
to allow the DLL to acquire and lock to the new rate.
Clock Jitter Considerations
High speed, high resolution ADCs are sensitive to the quality of the
clock input. The degradation in SNR at a given input frequency (f
due only to aperture jitter (t
In this equation, the rms aperture jitter represents the root mean
square of all jitter sources, including the clock input, analog input
signal, and ADC aperture jitter. IF undersampling applications
are particularly sensitive to jitter (see Figure 60).
The clock input should be treated as an analog signal in cases
where aperture jitter may affect the dynamic range of the AD9273.
Power supplies for clock drivers should be separated from the
ADC output driver supplies to avoid modulating the clock signal
with digital noise. Low jitter, crystal-controlled oscillators make
the best clock sources, such as the Valpey Fisher VFAC3 series.
If the clock is generated from another type of source (by gating,
dividing, or other methods), it should be retimed by the
original clock during the last step.
Refer to the AN-501 Application Note and the AN-756
Application Note for more in-depth information about how
jitter performance relates to ADCs (visit www.analog.com).
Power Dissipation and Power-Down Mode
As shown in Figure 62, the power dissipated by the AD9273 is
proportional to its sample rate. The digital power dissipation
does not vary much because it is determined primarily by the
DRVDD supply and bias current of the LVDS output drivers.
SNR Degradation = 20 × log 10[1/2 × π × f
130
120
100
110
90
80
70
60
50
40
30
Figure 60. Ideal SNR vs. Analog Input Frequency and Jitter
1
10 BITS
8 BITS
RMS CLOCK JITTER REQUIREMENT
ANALOG INPUT FREQUENCY (MHz)
10
J
) can be calculated by
0.125ps
0.25ps
0.5ps
1.0ps
2.0ps
100
A
× t
16 BITS
14 BITS
12 BITS
J
]
1000
Rev. B | Page 32 of 48
A
)
The AD9273 features scalable LNA bias currents (see Register 0x12
in Table 17). The default LNA bias current settings are high.
Figure 63 shows the typical reduction of AVDD2 current with
each bias setting. It is also recommended to adjust the LNA
offset using Register 0x10 (see Table 17) when the LNA bias
setting is low.
MID-HIGH
MID-LOW
Figure 63. AVDD2 Current at Different LNA Bias Settings, AD9273-40
HIGH
250
200
150
100
120
115
110
105
100
LOW
50
95
90
85
80
0
Figure 62. Power per Channel vs. f
0
0
Figure 61. Supply Current vs. f
0
I
AVDD1
I
AVDD1
20
, 50MSPS SPEED GRADE
10
10
, 25MSPS SPEED GRADE
40
SAMPLING FREQUENCY (MSPS)
SAMPLING FREQUENCY (MSPS)
50MSPS SPEED GRADE
TOTAL AVDD2 CURRENT (mA)
25MSPS SPEED GRADE
20
20
60
I
DRVDD
80
I
AVDD1
30
30
SAMPLE
100
SAMPLE
, 40MSPS SPEED GRADE
40MSPS SPEED GRADE
for f
120
for f
IN
40
40
= 5 MHz
IN
= 5 MHz
140
50
50
160
180