AD9389BBCPZ-165 Analog Devices Inc, AD9389BBCPZ-165 Datasheet - Page 7

• Manufacturer Part Number: AD9389BBCPZ-165
• Description: IC,TV/VIDEO CIRCUIT,Audio/Video Decoder For MPEG,CMOS,LLCC,64PIN,PLASTIC
• Manufacturer: Analog Devices Inc

Table 3. Pin Function Descriptions
LFCSP
2, 39 to 47,
50 to 63
6
3
4
5
18
20
7
8
9 to 12
13
14
26
21, 22
30, 31
27, 28
24, 25
32
19, 23, 29
1, 48, 49
15, 16, 17
N/A
64, paddle on
bottom side
36
35
37
38
2
Pin No.
LQFP
2, 50 to 58,
65 to 78
6
3
4
5
23
25
7
8
9 to 12
13
14
33
27, 28
37, 38
34, 35
30, 31
40
24, 29, 36,
41
1, 61 to 64
16, 19 to 21
15, 17, 18,
22, 26, 32,
39, 42, 43,
59, 60, 79,
80
N/A
47
46
48
49
2
Mnemonic
D[23:0]
CLK
DE
HSYNC
VSYNC
EXT_SWG
HPD
S/PDIF
MCLK
I
SCLK
LRCLK
PD/A0
TxC−/TxC+
Tx2−/Tx2+
Tx1−/Tx1+
Tx0−/Tx0+
INT
AVDD
DVDD
PVDD
GND
DGND
SDA
SCL
MDA
MCL
2
S[3:0]
Type
I
I
I
I
I
I
I
I
I
I
I
I
I
O
O
O
O
O
P
P
P
P
C
C
C
C
3
3
3
3
1
Description
Video Data Input. Digital input in RGB or YCbCr format. Supports CMOS logic levels from
1.8 V to 3.3 V.
Video Clock Input. Supports CMOS logic levels from 1.8 V to 3.3 V.
Data Enable Bit for Digital Video. Supports CMOS logic levels from 1.8 V to 3.3 V.
Horizontal Sync Input. Supports CMOS logic levels from 1.8 V to 3.3 V.
Vertical Sync Input. Supports CMOS logic levels from 1.8 V to 3.3 V.
Set Internal Reference Currents. Place 887 Ω resistor (1% tolerance) between this pin
and ground.
Hot Plug Detect Signal. This indicates to the interface whether the receiver is
connected. 1.8 V to 5.0 V CMOS logic levels.
S/PDIF (Sony/Philips Digital Interface) Audio Input. This is the audio input from a
Sony/Philips digital interface. Supports CMOS logic levels from 1.8 V to 3.3 V.
Audio Reference Clock. 128 × N × f
frequency (f
I
available through I
I
Left/Right Channel Selection. Supports CMOS logic levels from 1.8 V to 3.3 V.
Power-Down Control and I
are set by the PD/A0 pin state when the supplies are applied to the AD9389B. 1.8 V
to 3.3 V CMOS logic levels.
Differential Clock Output. Differential clock output at pixel clock rate; TMDS logic
level.
Differential Output Channel 2. Differential output of the red data at 10× the pixel
clock rate; TMDS logic level.
Differential Output Channel 1. Differential output of the green data at 10× the pixel
clock rate; TMDS logic level.
Differential Output Channel 0. Differential output of the blue data at 10× the pixel
clock rate; TMDS logic level.
Interrupt. Open drain. A 2 kΩ pull-up resistor to the microcontroller I/O supply is
recommended. Active Low.
1.8 V Power Supply for TMDS Outputs.
1.8 V Power Supply for Digital and I/O Power Supply. These pins supply power to the
digital logic and I/Os. They should be filtered and as quiet as possible.
1.8 V PLL Power Supply. The most sensitive portion of the AD9389B is the clock
generation circuitry. These pins provide power to the clock PLL. Provide quiet,
noise-free power to these pins.
Ground. The ground return for all circuitry on-chip. It is recommended that the
AD9389B be assembled on a single, solid ground plane with careful attention given
to ground current paths.
Ground. The ground return for all circuitry on-chip. It is recommended that the
AD9389B be assembled on a single, solid ground plane with careful attention given
to ground current paths.
Serial Port Data I/O. This pin serves as the serial port data I/O slave for register
access. Supports CMOS logic levels from 1.8 V to 3.3 V.
Serial Port Data Clock. This pin serves as the serial port data clock slave for register
access. Supports CMOS logic levels from 1.8 V to 3.3 V.
Serial Port Data I/O Master to HDCP Key EEPROM. Supports CMOS logic levels from
1.8 V to 3.3 V.
Serial Port Data Clock Master to HDCP Key EEPROM. Supports CMOS logic levels
from 1.8 V to 3.3 V.
2
2
S Audio Data Inputs. These represent the eight channels of audio (two per input)
S Audio Clock. Supports CMOS logic levels from 1.8 V to 3.3 V.
Rev. 0 | Page 7 of 12
S
), 256 × f
2
S. Supports CMOS logic levels from 1.8 V to 3.3 V.
S
, 384 × f
2
C Address Selection. The I
S
, or 512 × f
S
with N = 1, 2, 3, or 4. Set to 128 × sampling
S
. 1.8 V to 3.3 V CMOS logic levels.
2
C address and the PD polarity
AD9389B