AD9467BCPZ-250 Analog Devices Inc, AD9467BCPZ-250 Datasheet - Page 24

• Manufacturer Part Number: AD9467BCPZ-250
• Description: 16 Bit 250 MSPS ADC
• Manufacturer: Analog Devices Inc

Specifications of AD9467BCPZ-250

• Number Of Bits: 16
• Sampling Rate (per Second): 250M
• Data Interface: Serial, SPI™
• Number Of Converters: 1
• Power Dissipation (max): 1.45W
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 72-VFQFN, CSP Exposed Pad
• Number Of Elements: 1
• Resolution: 16Bit
• Architecture: Pipelined
• Sample Rate: 250MSPS
• Input Polarity: Bipolar
• Input Type: Voltage
• Rated Input Volt: ±1.25V
• Differential Input: Yes
• Power Supply Requirement: Single
• Single Supply Voltage (typ): 1.8/3.3V
• Dual Supply Voltage (typ): Not RequiredV
• Dual Supply Voltage (min): Not RequiredV
• Dual Supply Voltage (max): Not RequiredV
• Power Dissipation: 1.45W
• Differential Linearity Error: ±1LSB(Typ)
• Integral Nonlinearity Error: ±3LSB(Typ)
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 72
• Package Type: LFCSP EP
• Input Signal Type: Differential
• Sampling Rate: 250MSPS
• Input Channel Type: Differential
• Supply Voltage Range - Analog: 1.7V To 1.9V
• Supply Voltage Range - Digital: 1.7V To 1.9V
• Supply Current: 31mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9467
An example of the LVDS output using the ANSI-644 standard
(default) data eye and a time interval error (TIE) jitter histogram
with trace lengths of six inches on standard FR-4 material is shown
in Figure 65. It is the responsibility of the user to determine if
the waveforms meet the timing budget of the design.
Figure 65. Data Eye for LVDS Outputs in ANSI-644 Mode with 6-Inch Trace
Figure 64. Output Timing Example in LVDS Mode (Default), AD9467-250
–100
–200
–300
–400
1
2
3
400
300
200
100
14
12
10
0
8
6
4
2
0
–20
CH1
CH2
CH3
500mV Ω
500mV Ω
500mV Ω
–2
CLOCK
Lengths on Standard FR-4, AD9467-250
–10
DCO
DATA
–1
0
20.0GS/s
5.0ns/DIV
TIME (ns)
TIME (ps)
10
0
IT 25.0pt/pt
20
1
A CH2
30
2
10.0V
40
Rev. B | Page 24 of 32
The format of the output data is offset binary by default. An
example of the output coding format can be found in Table 8.
To change the output data format to twos complement or Gray
code, see the Memory Map section.
Table 8. Digital Output Coding
Code
65,536
32,768
32,767
0
An output clock is provided to assist in capturing data from the
AD9467. Data is clocked out of the AD9467 and must be
captured on the rising and falling edges of the DCO that supports
double data rate (DDR) capturing. See the timing diagram
shown in Figure 2 for more information.
When the SPI is used, the DCO phase can be adjusted in 100 ps
increments relative to the data edge. This enables the user to
refine system timing margins if required. The default DCO+
and DCO− timing, as shown in Figure 2, is 90° relative to the
output data edge.
Figure 66. Data Eye for LVDS Outputs in ANSI-644 Mode with 18-Inch Trace
–100
–200
–300
–400
400
300
200
100
50
45
40
35
30
25
20
15
10
0
5
0
–40
(VIN+) − (VIN−), Input
Span = 2.5 V p-p (V)
+1.25
0.00
−0.000038
−1.25
–2
Lengths on Standard FR-4, AD9467-250
–20
–1
0
TIME (ns)
TIME (ps)
0
Digital Output Offset Binary
(D15:D0)
1111 1111 1111 1111
1000 0000 0000 0000
0111 1111 1111 1111
0000 0000 0000 0000
20
1
40
2
60