AD9510-VCO/PCBZ Analog Devices Inc, AD9510-VCO/PCBZ Datasheet - Page 9

• Manufacturer Part Number: AD9510-VCO/PCBZ
• Description: 800MHz PLL Clock Dist Eval Bd.
• Manufacturer: Analog Devices Inc

Specifications of AD9510-VCO/PCBZ

• Main Purpose: Timing, Clock Distribution
• Utilized Ic / Part: AD9510
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

CLOCK OUTPUT PHASE NOISE
Table 5.
Parameter
CLK1-TO-LVPECL ADDITIVE PHASE NOISE
CLK1 = 622.08 MHz, OUT = 622.08 MHz
Divide Ratio = 1
CLK1 = 622.08 MHz, OUT = 155.52 MHz
Divide Ratio = 4
CLK1 = 622.08 MHz, OUT = 38.88 MHz
Divide Ratio = 16
CLK1 = 491.52 MHz, OUT = 61.44 MHz
Divide Ratio = 8
CLK1 = 491.52 MHz, OUT = 245.76 MHz
Divide Ratio = 2
CLK1 = 245.76 MHz, OUT = 61.44 MHz
Divide Ratio = 4
@ 10 Hz Offset
@ 100 Hz Offset
@ 1 kHz Offset
@ 10 kHz Offset
@ 100 kHz Offset
>1 MHz Offset
@ 10 Hz Offset
@ 100 Hz Offset
@ 1 kHz Offset
@ 10 kHz Offset
@ 100 kHz Offset
>1 MHz Offset
@ 10 Hz Offset
@ 100 Hz Offset
@ 1 kHz Offset
@ 10 kHz Offset
@ 100 kHz Offset
>1 MHz Offset
@ 10 Hz Offset
@ 100 Hz Offset
@ 1 kHz Offset
@ 10 kHz Offset
@ 100 kHz Offset
> 1 MHz Offset
@ 10 Hz Offset
@ 100 Hz Offset
@ 1 kHz Offset
@ 10 kHz Offset
@ 100 kHz Offset
>1 MHz Offset
@ 10 Hz Offset
@ 100 Hz Offset
@ 1 kHz Offset
@ 10 kHz Offset
@ 100 kHz Offset
>1 MHz Offset
Min
Rev. A | Page 9 of 60
−165
Typ
−125
−132
−140
−148
−153
−154
−128
−140
−148
−155
−161
−161
−135
−145
−158
−165
−165
−166
−131
−142
−153
−160
−165
−125
−132
−140
−151
−157
−158
−138
−144
−154
−163
−164
−165
Max
Unit
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Test Conditions/Comments
Distribution Section only; does not
include PLL or external VCO/VCXO
Input slew rate > 1 V/ns
AD9510