AD9518-1/PCBZ Analog Devices Inc, AD9518-1/PCBZ Datasheet - Page 14

• Manufacturer Part Number: AD9518-1/PCBZ
• Description: 6-Output Clock Generator With 2.8GHz
• Manufacturer: Analog Devices Inc

Specifications of AD9518-1/PCBZ

• Main Purpose: Timing, Clock Generator
• Utilized Ic / Part: AD9518-1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9518-1
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 19. Pin Function Descriptions
Pin No.
10, 24 to 26,
35, 37, 43, 45
21, 30, 31, 40
EPAD, 27, 34
1
2
3
4
5
6
7
8
9
11
12
13
14
15
16
17
18
42
41
39
38
Mnemonic
VS
VS_LVPECL
GND
REFMON
LD
VCP
CP
STATUS
REF_SEL
SYNC
LF
BYPASS
CLK
CLK
SCLK
CS
SDO
SDIO
RESET
PD
OUT0
OUT0
OUT1
OUT1
Description
3.3 V Power Pins.
Extended Voltage 2.5 V to 3.3 V LVPECL Power Pins.
Ground; External Paddle (EPAD).
Reference Monitor (Output). This pin has multiple selectable outputs; see Table 43, 0x1B.
Lock Detect (Output). This pin has multiple selectable outputs; see Table 43, 0x1A.
Power Supply for Charge Pump (CP); V
Charge Pump (Output). Connects to external loop filter.
Status (Output). This pin has multiple selectable outputs; see Table 43, 0x17.
Reference Select. Selects REF1 (low) or REF2 (high). This pin has an internal 30 kΩ pull-down resistor.
Manual Synchronizations and Manual Holdover. This pin initiates a manual synchronization and is also used
for manual holdover. Active low. This pin has an internal 30 kΩ pull-up resistor.
Loop Filter (Input). Connects to VCO control voltage node internally.
This pin is for bypassing the LDO to ground with a capacitor.
Along with CLK, this is the differential input for the clock distribution section.
Along with CLK, this is the differential input for the clock distribution section.
Serial Control Port Data Clock Signal.
Serial Control Port Chip Select; Active Low. This pin has an internal 30 kΩ pull-up resistor.
Serial Control Port Unidirectional Serial Data Out.
Serial Control Port Bidirectional Serial Data In/Out.
Chip Reset; Active Low. This pin has an internal 30 kΩ pull-up resistor.
Chip Power Down; Active Low. This pin has an internal 30 kΩ pull-up resistor.
LVPECL Output; One Side of a Differential LVPECL Output.
LVPECL Output; One Side of a Differential LVPECL Output.
LVPECL Output; One Side of a Differential LVPECL Output.
LVPECL Output; One Side of a Differential LVPECL Output.
REF_SEL
REFMON
BYPASS
STATUS
SYNC
VCP
CLK
CLK
LD
CP
VS
LF
10
11
12
1
2
3
4
5
6
7
8
9
PIN 1
INDICATOR
Figure 4. Pin Configuration
Rev. 0 | Page 14 of 64
(Not to Scale)
AD9518-1
TOP VIEW
S
< V
CP
< 5.0 V.
36
35
34
33
32
31
30
29
28
27
26
25
VS_LVPECL
VS_LVPECL
OUT3
OUT2
OUT2
OUT3