AD9518-1A/PCBZ Analog Devices Inc, AD9518-1A/PCBZ Datasheet

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AD9518-1A/PCBZ

Manufacturer Part Number
AD9518-1A/PCBZ
Description
6-Output Clock Generator With 2.8GHz
Manufacturer
Analog Devices Inc
Datasheet

Specifications of AD9518-1A/PCBZ

Main Purpose
Timing, Clock Generator
Embedded
No
Utilized Ic / Part
AD9518-1A
Primary Attributes
2 Inputs, 6 Outputs, 2.5GHz VCO
Secondary Attributes
LVPECL Output Logic
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
FEATURES
Low phase noise, phase-locked loop (PLL)
3 pairs of 1.6 GHz LVPECL outputs
Automatic synchronization of all outputs on power-up
Manual synchronization of outputs as needed
Serial control port
Available in 48-lead LFCSP
APPLICATIONS
Low jitter, low phase noise clock distribution
Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs
High performance wireless transceivers
10/40/100 Gb/sec networking line cards, including SONET,
High performance instrumentation
Broadband infrastructure
ATE
GENERAL DESCRIPTION
The AD9518-1
function with subpicosecond jitter performance, along with an on-
chip PLL and VCO. The on-chip VCO tunes from 2.30 GHz to
2.65 GHz. Optionally, an external VCO/VCXO of up to 2.4 GHz
can be used.
The AD9518-1 emphasizes low jitter and phase noise to
maximize data converter performance, and it can benefit other
applications with demanding phase noise and jitter requirements.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
On-chip VCO tunes from 2.30 GHz to 2.65 GHz
External VCO/VCXO to 2.4 GHz optional
1 differential or 2 single-ended reference inputs
Reference monitoring capability
Auto and manual reference switchover/holdover modes
Autorecover from holdover
Accepts LVPECL, LVDS, or CMOS references to 250 MHz
Programmable delays in path to PFD
Digital or analog lock detect, selectable
Each output pair shares a 1-to-32 divider with coarse
Additive output jitter 225 fs rms
Channel-to-channel skew paired outputs of <10 ps
Synchronous Ethernet, OTU2/3/4
phase delay
1
provides a multi-output clock distribution
6-Output Clock Generator with
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
The AD9518-1 features six LVPECL outputs (in three pairs).
The LVPECL outputs operate to 1.6 GHz.
Each pair of outputs has dividers that allow both the divide
ratio and coarse delay (or phase) to be set. The range of division
for the LVPECL outputs is 1 to 32.
The AD9518-1 is available in a 48-lead LFCSP and can be
operated from a single 3.3 V supply. An external VCO, which
requires an extended voltage range, can be accommodated
by connecting the charge pump supply (VCP) to 5 V. A separate
LVPECL power supply can be from 2.5 V to 3.3 V (nominal).
The AD9518-1 is specified for operation over the industrial
range of −40°C to +85°C.
1
AD9518 is used throughout to refer to all the members of the AD9518
family. However, when AD9518-1 is used, it is referring to that specific
member of the AD9518 family.
REFIN
CLK
FUNCTIONAL BLOCK DIAGRAM
SERIAL CONTROL PORT
Integrated 2.5 GHz VCO
REF1
REF2
DIGITAL LOGIC
©2007–2010 Analog Devices, Inc. All rights reserved.
AND
AND MUXs
DIVIDER
DIV/Φ
DIV/Φ
DIV/Φ
CP
Figure 1.
LVPECL
LVPECL
LVPECL
VCO
AD9518-1
LF
AD9518-1
MONITOR
STATUS
www.analog.com
OUT0
OUT1
OUT2
OUT3
OUT4
OUT5

Related parts for AD9518-1A/PCBZ

AD9518-1A/PCBZ Summary of contents

Page 1

... The AD9518-1 is specified for operation over the industrial range of −40°C to +85°C. 1 AD9518 is used throughout to refer to all the members of the AD9518 family. However, when AD9518-1 is used referring to that specific member of the AD9518 family. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. ...

Page 2

... Control Registers ............................................................................ 45 Control Register Map Overview .............................................. 45   Control Register Map Descriptions ......................................... 47   Applications Information .............................................................. 60   Frequency Planning Using the AD9518 .................................. 60   Using the AD9518 Outputs for ADC Clock Applications .... 60   LVPECL Clock Distribution ..................................................... 61   Outline Dimensions ....................................................................... 62   Ordering Guide .......................................................................... 62   Rev Page   ...

Page 3

... Changes to Table 44 ........................................................................ 48 Changes to Table 45 ........................................................................ 55 Changes to Table 46 ........................................................................ 57 Changes to Table 47 ........................................................................ 58 Changes to Table 48 ........................................................................ 59 Added Frequency Planning Using the AD9518 Section ............ 60 Changes to LVDS Clock Distribution Section ............................ 61 Changes to Figure 52 and Figure 54; Added Figure 53 .............. 61 Added Exposed Paddle Notation to Outline Dimensions; Changes to Ordering Guide ........................................................... 62 9/07— ...

Page 4

... AD9518-1 SPECIFICATIONS Typical (typ) is given for 3.3 V ± 5 S_LVPECL Minimum (min) and maximum (max) values are given over full V POWER SUPPLY REQUIREMENTS Table 1. Parameter S_LVPECL V CP RSET Pin Resistor CPRSET Pin Resistor BYPASS Pin Capacitor PLL CHARACTERISTICS Table 2. Parameter VCO (ON-CHIP) ...

Page 5

... Register 0x017[1:0] = 00b, 01b, 11b; Register 0x018[ 3.5 ns Register 0x017[1:0] = 10b; Register 0x018[ Register 0x017[1:0] = 00b, 01b, 11b; Register 0x018[ Register 0x017[1:0] = 00b, 01b, 11b; Register 0x018[ Register 0x017[1:0] = 10b; Register 0x018[ Rev Page 5.1 kΩ RSET = < V − 0 < V − 0 AD9518 PFD ...

Page 6

... AD9518-1 CLOCK INPUTS Table 3. Parameter CLOCK INPUTS (CLK, CLK) Input Frequency Input Sensitivity, Differential Input Level, Differential Input Common-Mode Voltage Input Common-Mode Range, V CMR Input Sensitivity, Single-Ended Input Resistance Input Capacitance 1 Below about 1 MHz, the input should be dc-coupled. Care should be taken to match V CLOCK OUTPUTS Table 4 ...

Page 7

... Internal VCO; direct to LVPECL output −46 dBc/Hz −76 dBc/Hz −104 dBc/Hz −123 dBc/Hz −140 dBc/Hz −146 dBc/Hz −47 dBc/Hz −77 dBc/Hz −105 dBc/Hz −124 dBc/Hz −141 dBc/Hz −146 dBc/Hz −54 dBc/Hz −78 dBc/Hz −106 dBc/Hz −125 dBc/Hz −141 dBc/Hz −146 dBc/Hz Rev Page AD9518-1 ...

Page 8

... AD9518-1 CLOCK OUTPUT ABSOLUTE TIME JITTER (CLOCK GENERATION USING INTERNAL VCO) Table 8. Parameter LVPECL OUTPUT ABSOLUTE TIME JITTER VCO = 2.46 GHz; LVPECL = 491.52 MHz; PLL LBW = 55 kHz VCO = 2.46 GHz; LVPECL = 122.88 MHz; PLL LBW = 55 kHz VCO = 2.46 GHz; LVPECL = 61.44 MHz; PLL LBW = 55 kHz CLOCK OUTPUT ABSOLUTE TIME JITTER (CLOCK CLEANUP USING INTERNAL VCO) Table 9 ...

Page 9

... Calculated from SNR of ADC method; DCC on Min Typ Max Unit Test Conditions/Comments Distribution section only; does not include PLL and VCO; uses rising edge of clock signal 210 fs rms Calculated from SNR of ADC method Rev Page AD9518-1 ...

Page 10

... AD9518-1 SERIAL CONTROL PORT Table 13. Parameter CS (INPUT) Input Logic 1 Voltage Input Logic 0 Voltage Input Logic 1 Current Input Logic 0 Current Input Capacitance SCLK (INPUT) Input Logic 1 Voltage Input Logic 0 Voltage Input Logic 1 Current Input Logic 0 Current Input Capacitance SDIO (WHEN INPUT) Input Logic 1 Voltage ...

Page 11

... All references off to REF1 or REF2 enabled; differential reference not enabled 70 mW CLK input selected to VCO selected 75 mW PLL off to PLL on, normal operation; no reference enabled 30 mW Divider bypassed to divide-by-2 to divide-by-32 160 mW No LVPECL output on to one LVPECL output Second LVPECL output turned on, same channel Rev Page AD9518-1 ...

Page 12

... AD9518-1 TIMING DIAGRAMS t CLK CLK t PECL Figure 2. CLK/ CLK to Clock Output Timing, DIV = 1 DIFFERENTIAL 80% 20 Figure 3. LVPECL Timing, Differential Rev Page LVPECL t FP ...

Page 13

... V Table 18. S −0 0.3 V Package Type S 48-Lead LFCSP 1 Thermal impedance measurements were taken on a 4-layer board in still air −0 0 accordance with EIA/JESD51-2. S −0 0 150°C ESD CAUTION −65°C to +150°C 300°C Rev Page AD9518-1 1 θ Unit JA 24.7 °C/W ...

Page 14

... I Differential clock input 12 I Differential clock input 1 PIN INDICATOR VCP STATUS 5 AD9518-1 6 TOP VIEW SYNC 7 (Not to Scale BYPASS CLK 11 CLK 12 CONNECTED TO GROUND FOR PROPER OPERATION. Figure 4. Pin Configuration Mnemonic Description REFMON Reference Monitor (Output). This pin has multiple selectable outputs; see Table 44, Register 0x1B ...

Page 15

... Alternatively, this pin is a single-ended input for REF2. Along with REFIN, this is the (self-biased) differential input for the PLL reference. Alternatively, this pin is a single-ended input for REF1. Ground. The external paddle on the bottom of the package must be connected to ground for proper operation. Rev Page AD9518-1 ...

Page 16

... AD9518-1 TYPICAL PERFORMANCE CHARACTERISTICS 300 3 CHANNELS—6 LVPECL 280 260 240 220 200 3 CHANNELS—3 LVPECL 180 160 2 CHANNELS—2 LVPECL 140 120 1 CHANNEL—1 LVPECL 100 0 500 1000 1500 FREQUENCY (MHz) Figure 5. Current vs. Frequency, Direct-to-Output, LVPECL Outputs 2.3 2.4 2.5 VCO FREQUENCY (GHz) Figure 6 ...

Page 17

... SPAN 50MHz 1600 1400 1200 1000 800 SPAN 1MHz Rev Page AD9518 TIME (ns) Figure 14. LVPECL Output (Differential) @ 100 MHz 0 1 TIME (ns) Figure 15. LVPECL Output (Differential) @ 1600 MHz FREQUENCY (GHz) Figure 16. LVPECL Differential Swing vs. Frequency ...

Page 18

... AD9518-1 –70 –80 –90 –100 –110 –120 –130 –140 –150 10k 100k 1M FREQUENCY (Hz) Figure 17. Internal VCO Phase Noise (Absolute) Direct to LVPECL @ 2650 MHz –70 –80 –90 –100 –110 –120 –130 –140 –150 10k 100k 1M FREQUENCY (Hz) Figure 18. Internal VCO Phase Noise (Absolute) Direct to LVPECL @ 2475 MHz – ...

Page 19

... PFD = 19.44 MHz; LBW = 12.8 kHz; LVPECL Output = 155.52 MHz –120 –130 –140 –150 –160 10M 100M 1k Figure 25. Phase Noise (Absolute); External VCXO (Toyocom TCO-2112) @ 245.76 MHz; PFD = 15.36 MHz; LBW = 250 Hz; LVPECL Output = 245.76 MHz 10M 100M Rev Page AD9518-1 10k 100k 1M 10M 100M FREQUENCY (Hz) ...

Page 20

... AD9518-1 TERMINOLOGY Phase Jitter and Phase Noise An ideal sine wave can be thought of as having a continuous and even progression of phase with time from 0° to 360° for each cycle. Actual signals, however, display a certain amount of variation from ideal phase progression over time. This phenomenon is called phase jitter ...

Page 21

... DIVIDER R DELAY VCO STATUS PROGRAMMABLE A/B PRESCALER COUNTERS N DELAY N DIVIDER DIVIDE DIVIDE DIVIDE DIVIDE Figure 26. Detailed Block Diagram Rev Page AD9518-1 CPRSET VCP LD LOCK DETECT HOLD PHASE CHARGE FREQUENCY CP PUMP DETECTOR STATUS OUT0 OUT0 LVPECL OUT1 OUT1 OUT2 OUT2 LVPECL OUT3 ...

Page 22

... AD9518-1 THEORY OF OPERATION OPERATIONAL CONFIGURATIONS The AD9518 can be configured in several ways. These configurations must be set up by loading the control registers (see Table 42 and Table 43 through Table 49). Each section or function must be individually programmed by setting the appropriate bits in the corresponding control register or registers. ...

Page 23

... REFMON DISTRIBUTION REFERENCE R PROGRAMMABLE DIVIDER R DELAY VCO STATUS PROGRAMMABLE A/B N DELAY COUNTERS N DIVIDER DIVIDE BY 0 DIVIDE DIVIDE DIVIDE Rev Page AD9518-1 CPRSET VCP LD LOCK DETECT HOLD PHASE CHARGE FREQUENCY CP PUMP DETECTOR STATUS OUT0 OUT0 LVPECL OUT1 OUT1 OUT2 OUT2 LVPECL OUT3 ...

Page 24

... LOW DROPOUT BYPASS REGULATOR (LDO) LF VCO CLK CLK PD DIGITAL SYNC LOGIC RESET SCLK SERIAL SDIO CONTROL SDO PORT CS AD9518-1 Table 23. Settings When Using an Internal VCO Register 0x010[1:0] = 00b 0x010 to 0x01E 0x018[0] = 0b, 0x232[ 0x1E0[2:0] 0x1E1[ 0x1E1[ 0x018[0] = 1b, 0x232[ GND RSET REFMON DISTRIBUTION REFERENCE R ...

Page 25

... VCO/VCXO being used. Table 26. Setting the PFD Polarity Register 0x010[ 0x010[ After the appropriate register values are programmed, Register 0x232 must be set to 0x01 for the values to take effect. Rev Page AD9518-1 CPRSET VCP LD LOCK DETECT HOLD PHASE CHARGE ...

Page 26

... ADIsimCLK™ (V1.2 or later free program that can help with the design and exploration of the capabilities and features of the AD9518, including the design of the PLL loop filter available at www.analog.com/clocks. Phase Frequency Detector (PFD) The PFD takes inputs from the R counter and N counter and produces an output proportional to the phase and frequency difference between them ...

Page 27

... PUMP Figure 32. Example of External Loop Filter for a PLL Using an External VCO PLL Reference Inputs The AD9518 features a flexible PLL reference input circuit that allows either a fully differential input or two separate single-ended inputs. The input frequency range for the reference inputs is specified in Table 2. Both the differential and the single-ended inputs are self-biased, allowing for easy ac coupling of input signals ...

Page 28

... A and B. The total divider value × where P can 16, or 32. Prescaler The prescaler of the AD9518 allows for two modes of operation: a fixed divide (FD) mode and a dual modulus (DM) mode where the prescaler divides by P and ( and 3, 4 and 5, 8 and 9, 16 and 17 and 33}. The prescaler modes of operation are given in Table 44, Register 0x016[2:0] ...

Page 29

... VCO frequency is greater than 2400 MHz because the frequency going to the A/B counter is too high. When the AD9518 B counter is bypassed (B = 1), the A counter should be set to 0, and the overall resulting divide is equal to the prescaler setting, P. The possible divide ratios in this mode are 16, and 32 ...

Page 30

... The number of consecutive PFD cycles required for lock is programmable (Register 0x018[6:5]). Analog Lock Detect (ALD) The AD9518 provides an ALD function that can be selected for use at the LD pin. There are two versions of ALD, as follows: • N-channel open-drain lock detect. This signal requires a pull-up resistor to the positive supply, VS ...

Page 31

... Holdover The AD9518 PLL has a holdover function. Holdover is implemented by putting the charge pump into a high impedance state. This is useful when the PLL reference clock is lost. Holdover mode allows the VCO to maintain a relatively constant frequency even though there is no reference clock. Without this function, the charge pump is placed into a constant pump-up or pump-down state, resulting in a massive VCO frequency shift ...

Page 32

... Register 0x01D[0] = 1b; enable the holdover function. Frequency Status Monitors The AD9518 contains three frequency status monitors that are used to indicate if the PLL reference (or references in the case of single-ended mode) and the VCO have fallen below a threshold frequency. A diagram showing their location in the PLL is shown in Figure 38 ...

Page 33

... VCO CLK CLK VCO Calibration The AD9518 on-chip VCO must be calibrated to ensure proper operation over process and temperature. The VCO calibration is controlled by a calibration controller running off of a divided REFIN clock. The calibration requires that the PLL be set up properly to lock the PLL loop and that the REFIN clock be present. ...

Page 34

... Internal VCO or External CLK as Clock Source The clock distribution of the AD9518 has two clock input sources: an internal VCO or an external clock connected to the CLK/ CLK pins. Either the internal VCO or CLK must be chosen as the source of the clock signal to distribute ...

Page 35

... Table 33. Duty Cycle with VCO Divider, Input Duty Cycle Is 50% VCO Divider 1 Even Odd = 3 Bypass DCCOFF 0x191[7] 0x192[0] Odd = 5 0x194[7] 0x195[0] 0x197[7] 0x198[0] Even, Odd Even, Odd Rev Page AD9518 set by the values of M and This allows X D Output Duty Cycle DCCOFF = 1 DCCOFF = 0 1 (divider 50% 50% bypassed) 1 (divider 33 ...

Page 36

... DIVIDER 0 DIVIDER 1 DIVIDER 2 Synchronizing the Outputs—SYNC Function The AD9518 clock outputs can be synchronized to each other. Outputs can be individually excluded from synchronization. Synchronization consists of setting the nonexcluded outputs to a preset set of static conditions and subsequently releasing these outputs to continue clocking at the same instant with the preset conditions applied ...

Page 37

... VCO divider) and an uncertainty one cycle of the clock at the input to the channel divider due to the asynchronous nature of the SYNC signal with respect to the clock edges inside the AD9518. The delay from the output clocking is between 14 and 15 cycles of clock at the channel divider input, plus either one cycle of the VCO divider input ...

Page 38

... LVPECL output circuitry from damage that could be caused by certain termination and load configurations when tristated. Because this is not a complete power-down, it can be called sleep mode. OUT When the AD9518 power-down, the chip is in the following state: OUT • The PLL is off (asynchronous power-down). ...

Page 39

... Synchronizing the Outputs—SYNC Function section). A VCO calibration is not required when exiting power-down. PLL Power-Down The PLL section of the AD9518 can be selectively powered down. There are three PLL operating modes set by Register 0x010[1:0], as shown in Table 44. In asynchronous power-down mode, the device powers down as soon as the registers are updated ...

Page 40

... PORT SDIO 16 Figure 43. Serial Control Port GENERAL OPERATION OF SERIAL CONTROL PORT A write or a read operation to the AD9518 is initiated by pulling CS low. CS stalled high is supported in modes where three or fewer bytes of data (plus instruction data) are transferred (see CS can temporarily return high on any byte ...

Page 41

... In MSB first mode, subsequent bytes decrement the address. MSB/LSB FIRST TRANSFERS The AD9518 instruction word and byte data can be MSB first or LSB first. Any data written to Register 0x000 must be mirrored; the upper four bits (Bits[7:4]) must mirror the lower four bits (Bits[3:0]) ...

Page 42

... AD9518-1 Table 39. Serial Control Port, 16-Bit Instruction Word, MSB First MSB I15 I14 I13 I12 W1 W0 A12 = 0 R/W CS SCLK DON'T CARE SDIO R A12 A11 A10 DON'T CARE 16-BIT INSTRUCTION HEADER Figure 45. Serial Control Port Write—MSB First, 16-Bit Instruction, Two Bytes Data ...

Page 43

... Minimum period that SCLK should logic high state HIGH t Minimum period that SCLK should logic low state LOW t SCLK to valid SDIO and SDO (see Figure 48 CLK t t HIGH LOW t DH BIT N BIT Figure 50. Serial Control Port Timing—Write Rev Page AD9518 ...

Page 44

... Junction-to-case thermal resistance (die-to-heat sink) per MIL-STD-883, Method 1012.1 JC Ψ Junction-to-top-of-package characterization parameter, natural convection per JEDEC JESD51-2 (still air) JT The AD9518 is specified for a case temperature (T that T is not exceeded, an airflow source can be used. CASE Use the following equation to determine the junction ...

Page 45

... REF1 Differential power-on power-on reference Holdover External Holdover enable holdover enable control REF2 REF1 Digital frequency > frequency > lock detect threshold threshold AD9518-1 Default Value (Hex) 0x18 0x61 0x00 0x7D 0x01 0x00 0x00 0x03 0x00 0x06 0x00 0x06 0x00 0x00 0x00 0x00 ...

Page 46

... AD9518-1 Reg. Addr. (Hex) Parameter Bit 7 (MSB) Bit 6 LVPECL Outputs 0x0F0 OUT0 0x0F1 OUT1 0x0F2 OUT2 0x0F3 OUT3 0x0F4 OUT4 0x0F5 OUT5 0x0F6 to 0x13F 0x140 to 0x143 0x144 to 0x18F LVPECL Channel Dividers 0x190 Divider 0 (PECL) 0x191 Divider 0 Divider 0 bypass nosync 0x192 Blank ...

Page 47

... Selects unidirectional or bidirectional data transfer mode. 0: SDIO pin used for write and read; SDO set to high impedance; bidirectional mode (default). 1: SDO used for read, SDIO used for write; unidirectional mode. Uniquely identifies the dash version (-0 through -4) of the AD9518. AD9518-0: 0x21. AD9518-1: 0x61. ...

Page 48

... AD9518-1 Table 44. PLL Reg. Addr. (Hex) Bits Name Description 0x010 7 PFD polarity Sets the PFD polarity. Negative polarity is for use (if needed) with external VCO/VCXO only. The on-chip VCO requires positive polarity; Bit positive; higher control voltage produces higher frequency (default). 1: negative; higher control voltage produces lower frequency. ...

Page 49

... AND (status of selected reference) AND (status of VCO LVL Status of VCO frequency; active low LVL Selected reference (low = REF2, high = REF1 LVL Digital lock detect (DLD); active low LVL Holdover active; active low LVL LD pin comparator output; active low. Rev Page AD9518-1 ...

Page 50

... AD9518-1 Reg. Addr. (Hex) Bits Name Description 0x017 [1:0] Antibacklash 1 pulse width 0x018 [6:5] Lock detect Required consecutive number of PFD cycles with edges inside lock detect window before the DLD indicates a locked counter condition Digital lock detect If the time difference of the rising edges at the inputs to the PFD is less than the lock detect window time, the digital lock window detect flag is set ...

Page 51

... LVL Status of VCO frequency; active low LVL Selected reference (low = REF2, high = REF1 LVL Digital lock detect (DLD); active low LVL Holdover active; active low LVL Not available. Do not use. Rev Page REF1, REF2, and VCO frequency status monitor). AD9518-1 ...

Page 52

... AD9518-1 Reg. Addr. (Hex) Bits Name Description 0x01B 7 VCO Enables or disables VCO frequency monitor. frequency monitor 0: disables VCO frequency monitor (default). 1: enables VCO frequency monitor. 6 REF2 ( REFIN ) Enables or disables REF2 frequency monitor. frequency monitor 0: disables REF2 frequency monitor (default). 1: enables REF2 frequency monitor. ...

Page 53

... VCO frequency is less than the threshold. 1: VCO frequency is greater than the threshold. Figure 37 ). Otherwise, this function can be used with the REFMON and Figure 37 Rev Page AD9518-1 ). This is not the same as holdover enabled. Table 15 , REF1, REF2, and VCO ...

Page 54

... AD9518-1 Reg. Addr. (Hex) Bits Name Description 0x01F 2 REF2 frequency > Read-only register. Indicates if the frequency of the signal at REF2 is greater than the threshold frequency set by threshold Register 0x1A, Bit 6. 0: REF2 frequency is less than threshold frequency. 1: REF2 frequency is greater than threshold frequency. ...

Page 55

... Mode 0 0 Normal operation (default Partial power-down, reference on; use only if there are no external load resistors Partial power-down, reference on, safe LVPECL power-down Total power-down, reference off; use only if there are no external load resistors. Rev Page AD9518 Output On Off Off Off Output On Off ...

Page 56

... AD9518-1 Reg. Addr. (Hex) Bits Name 0x0F3 4 OUT3 invert [3:2] OUT3 LVPECL differential voltage [1:0] OUT3 power-down 0x0F4 4 OUT4 invert [3:2] OUT4 LVPECL differential voltage [1:0] OUT4 power-down 0x0F5 4 OUT5 invert [3:2] OUT5 LVPECL differential voltage [1:0] OUT5 power-down Description Sets the output polarity. ...

Page 57

... OUT2 and OUT3 are connected to Divider 1 (default Register 0x1E1[1:0] = 10b, the VCO is routed directly to OUT2 and OUT3. If Register 0x1E1[1:0] = 00b, the CLK is routed directly to OUT2 and OUT3. If Register 0x1E1[1:0] = 01b, there is no effect. Duty-cycle correction function. 0: enables duty-cycle correction (default). 1: disables duty-cycle correction. Rev Page AD9518-1 ...

Page 58

... AD9518-1 Reg. Addr. (Hex) Bits Name 0x196 [7:4] Divider 2 low cycles [3:0] Divider 2 high cycles 0x197 7 Divider 2 bypass 6 Divider 2 nosync 5 Divider 2 force high 4 Divider 2 start high [3:0] Divider 2 phase offset 0x198 1 Divider 2 direct to output 0 Divider 2 DCCOFF Table 47. VCO Divider and CLK Input Reg ...

Page 59

... This bit must be set transfer the contents of the buffer registers into the active registers, which happens on the next SCLK rising edge. This bit is self-clearing; that is, it does not have to be set back (self-clearing): updates all active registers to the contents of the buffer registers. Rev Page AD9518-1 ...

Page 60

... MHz offset) for the same output frequency is usually less than 150 fs over the entire VCO frequency range (1.45 GHz to 2.95 GHz) of the AD9518 family. If the desired frequency plan can be achieved with a version of the AD9518 that has a lower VCO frequency, choosing the lower frequency part results in the lowest phase noise and the lowest jitter ...

Page 61

... LVPECL CLOCK DISTRIBUTION The LVPECL outputs of the AD9518 provide the lowest jitter clock signals available from the AD9518. The LVPECL outputs (because they are open emitter) require a dc termination to bias the output transistors. The simplified equivalent circuit in Figure 42 shows the LVPECL output stage. ...

Page 62

... AD9518-1ABCPZ −40°C to +85°C 2 AD9518-1ABCPZ-RL7 −40°C to +85°C AD9518-1BCPZ −40°C to +85°C AD9518-1BCPZ-REEL7 −40°C to +85°C 2 AD9518-1A/PCBZ AD9518-1/PCBZ RoHS Compliant Part. 2 Recommended for use in new designs; reference PCN 09_156. 0.60 MAX 7.00 BSC SQ 0.60 MAX 0.50 BSC 6 ...

Page 63

... NOTES Rev Page AD9518-1 ...

Page 64

... AD9518-1 NOTES ©2007–2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06430-0-1/10(A) Rev Page ...

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