AD9520-3BCPZ Analog Devices Inc, AD9520-3BCPZ Datasheet - Page 32
![12/24 Channel Clock Gen 2,0GH](/photos/6/50/65021/505-64-lfcsp_sml.jpg)
AD9520-3BCPZ
Manufacturer Part Number
AD9520-3BCPZ
Description
12/24 Channel Clock Gen 2,0GH
Manufacturer
Analog Devices Inc
Type
Clock Generator, Fanout Distributionr
Datasheet
1.AD9520-3BCPZ.pdf
(84 pages)
Specifications of AD9520-3BCPZ
Design Resources
Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers (CN0121) Phase Coherent FSK Modulator (CN0186)
Pll
Yes
Input
CMOS, LVDS, LVPECL
Output
CMOS, LVPECL
Number Of Circuits
1
Ratio - Input:output
2:12, 2:24
Differential - Input:output
Yes/Yes
Frequency - Max
2.25GHz
Divider/multiplier
Yes/No
Voltage - Supply
3.135 V ~ 3.465 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
64-LFCSP
Frequency-max
2.25GHz
Function
Clock Generator
Operating Temperature (max)
85C
Operating Temperature (min)
-40C
Package Type
LFCSP EP
Pin Count
64
Mounting
Surface Mount
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
AD9520-3
Mode 2: High Frequency Clock Distribution—CLK or
External VCO > 1600 MHz
The AD9520 power-up default configuration has the PLL
powered off and the routing of the input set so that the CLK/
CLK input is connected to the distribution section through the
VCO divider (divide-by-1/divide-by-2/divide-by-3/ divide-by-4/
divide-by-5/divide-by-6). This is a distribution only mode that
allows for an external input up to 2400 MHz (see
maximum frequency that can be applied to the channel dividers
is 1600 MHz; therefore, higher input frequencies must be divided
down before reaching the channel dividers.
When the PLL is enabled, this routing also allows the use of the
PLL with an external VCO or VCXO with a frequency <2400 MHz.
In this configuration, the internal VCO is not used and is powered
off. The external VCO/VCXO feeds directly into the prescaler.
The register settings shown in Table 26 are the default values of
these registers at power-up or after a reset operation.
Table 3
). The
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Table 26. Default Register Settings for Clock Distribution
Mode
Register
0x010[1:0] = 01b
0x1E0[2:0] = 000b
0x1E1[0] = 0b
0x1E1[1] = 0b
When using the internal PLL with an external VCO, the PLL
must be turned on.
Table 27. Settings When Using an External VCO
Register
0x010[1:0] = 00b
0x010 to 0x01E
0x1E1[1] = 0b
An external VCO requires an external loop filter that must be
connected between CP and the tuning pin of the VCO. This
loop filter determines the loop bandwidth and stability of the
PLL. Make sure to select the proper PFD polarity for the VCO
being used.
Table 28. Setting the PFD Polarity
Register
0x010[7] = 0b
0x010[7] = 1b
CLK selected as the source
Description
PLL normal operation (PLL on)
PLL settings; select and enable a
reference input; set R, N (P, A, B), PFD
polarity, and I
loop configuration
Description
PLL asynchronous power-down (PLL off )
Set VCO divider = 2
Use the VCO divider
CLK selected as the source
Description
PFD polarity positive (higher control
voltage produces higher frequency)
PFD polarity negative (higher control
voltage produces lower frequency)
CP
according to the intended