AD9520-4BCPZ Analog Devices Inc, AD9520-4BCPZ Datasheet - Page 48

• Manufacturer Part Number: AD9520-4BCPZ
• Description: Clock IC With 1.6GHz On-chip VCO
• Manufacturer: Analog Devices Inc
• Type: Clock Generator, Fanout Distributionr

Specifications of AD9520-4BCPZ

• Design Resources: Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers (CN0121) Phase Coherent FSK Modulator (CN0186)
• Pll: Yes
• Input: CMOS, LVDS, LVPECL
• Output: CMOS, LVPECL
• Number Of Circuits: 1
• Ratio - Input:output: 2:12, 2:24
• Differential - Input:output: Yes/Yes
• Frequency - Max: 1.8GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LFCSP
• Frequency-max: 1.8GHz
• Function: Clock Generator
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Package Type: LFCSP EP
• Pin Count: 64
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9520-4/PCBZ - BOARD EVAL FOR AD9520-4
• Lead Free Status / Rohs Status: Compliant

AD9520-4
INPUT TO CHANNEL DIVIDER
LVPECL Output Drivers
The LVPECL differential voltage (V
~400 mV to 960 mV, see Bit 1 and Bit 2 in Register 0x0F0 to
Register 0x0FB. The LVPECL outputs have dedicated pins for
power supply (VS_DRV), allowing a separate power supply to
be used. VS_DRV can be from 2.5 V to 3.3 V.
The LVPECL output polarity can be set as noninverting or
inverting, which allows for the adjustment of the relative
polarity of outputs within an application without requiring a
board layout change. Each LVPECL output can be powered
down or powered up as needed. Because of the architecture of
the LVPECL output stages, there is the possibility of electrical
overstress and breakdown under certain power-down conditions.
For this reason, the LVPECL outputs have two power-down
modes: total power-down and safe power-down.
SYNC PIN
SYNC PIN
INPUT TO CHANNEL DIVIDER
CHANNEL DIVIDER
INPUT TO VCO DIVIDER
OUTPUT CLOCKING
CHANNEL DIVIDER
INPUT TO CLK
CHANNEL DIVIDER
OUTPUT CLOCKING
OUTPUT OF
CHANNEL DIVIDER
OUTPUT OF
Figure 49. SYNC Timing Pipeline Delay When VCO Divider Is Used—CLK or VCO Is Input
Figure 50. SYNC Timing Pipeline Delay When VCO Divider Is Not Used—CLK Input Only
OD
) is selectable (from
1
14 TO 15 CYCLES AT CHANNEL DIVIDER INPUT + 1 CYCLE AT CLK INPUT
1
14 TO 15 CYCLES AT CHANNEL DIVIDER INPUT + 1 CYCLE AT VCO DIVIDER INPUT
2
2
3
CHANNEL DIVIDER OUTPUT STATIC
3
CHANNEL DIVIDER OUTPUT STATIC
4
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4
5
5
6
6
In total power-down mode, all output drivers are shut off
simultaneously. This mode must not be used if there is an
external voltage bias network (such as Thevenin equivalent
termination) on the output pins that will cause a dc voltage to
appear at the powered down outputs. However, total power-
down mode is allowed when the LVPECL drivers are terminated
using only pull-down resistors. The total power-down mode is
activated by setting 0x230[1].
The primary power-down mode is the safe power-down mode.
This mode continues to protect the output devices while powered
down. There are three ways to activate safe power-down mode:
individually set the power-down bit for each driver, power down an
individual output channel (all of the drivers associated with that
channel are powered down automatically), and activate sleep mode.
7
7
8
8
9
9
10
10
11
11
12
12
13
14
13
1
14
1
OUTPUT CLOCKING
CHANNEL DIVIDER
OUTPUT CLOCKING
CHANNEL DIVIDER