AD9520-5BCPZ Analog Devices Inc, AD9520-5BCPZ Datasheet - Page 73

• Manufacturer Part Number: AD9520-5BCPZ
• Description: 12/24-Output Clock Generator
• Manufacturer: Analog Devices Inc
• Type: Clock Generator, Fanout Distributionr

Specifications of AD9520-5BCPZ

• Design Resources: Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers (CN0121) Phase Coherent FSK Modulator (CN0186)
• Pll: Yes
• Input: CMOS, LVDS, LVPECL
• Output: CMOS, LVPECL
• Number Of Circuits: 1
• Ratio - Input:output: 2:12, 2:24
• Differential - Input:output: Yes/Yes
• Frequency - Max: 2.4GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LFCSP
• Frequency-max: 1.6GHz
• Function: Clock Generator
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Package Type: LFCSP EP
• Pin Count: 64
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Reg.
Addr
(Hex) Bit(s) Name
1E0
1E1
1E1
Table 51. VCO Divider and CLK Input
Table 52. System
Reg.
Addr
(Hex) Bit(s) Name
230
230
230
230
Table 53. Update All Registers
Reg.
Addr
(Hex) Bit(s) Name
232
[2:0]
[4]
[0]
[0]
[3]
[2]
[1]
[0]
VCO divider
Power-down clock input section Powers down the clock input section (including the CLK buffer, VCO divider, and CLK tree).
Bypass VCO divider
IO_UPDATE
Disable power-on SYNC
Power-down SYNC
Power-down distribution reference
Soft SYNC
Description
This bit must be set to 1 to transfer the contents of the buffer registers into the active registers. This happens
on the next SCLK rising edge. This bit is self-clearing; that is, it does not have to be set back to 0.
[0] = 1 (self-clearing); update all active registers to the contents of the buffer registers.
Description
[2]
0
0
0
0
1
1
1
1
[4] = 0; normal operation (default).
[4] = 1; power down.
Bypasses or uses the VCO divider.
[0] = 0; use the VCO divider (default).
[0] = 1; bypass the VCO divider.
Description
Power-on SYNC mode. Used to disable the antiruntpulse circuitry.
[3] = 0; enable the antiruntpulse circuitry (default).
[3] = 1; disable the antiruntpulse circuitry.
Powers down the SYNC function.
[2] = 0; normal operation of the SYNC function (default).
[2] = 1; power-down SYNC circuitry.
Powers down the reference for the distribution section.
[1] = 0; normal operation of the reference for the distribution section (default).
[1] = 1; powers down the reference for the distribution section.
The soft SYNC bit works in the same way as the SYNC pin, except that the polarity of
the bit is reversed; that is, a high level forces selected channels into a predetermined
static state, and a 1-to-0 transition triggers a SYNC.
[0] = 0; same as SYNC high.
[0] = 1; same as SYNC low.
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[1]
0
0
1
1
0
0
1
1
[0]
0
1
0
1
0
1
0
1
Divide
2 (default)
3
4
5
6
Output static
1 (bypass)
Output static
AD9520-5