AD9522-0BCPZ Analog Devices Inc, AD9522-0BCPZ Datasheet - Page 74
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AD9522-0BCPZ
Manufacturer Part Number
AD9522-0BCPZ
Description
12- Channel Clock Generator With Integra
Manufacturer
Analog Devices Inc
Type
Clock Generator, Fanout Distributionr
Datasheet
1.AD9522-0BCPZ-REEL7.pdf
(84 pages)
Specifications of AD9522-0BCPZ
Pll
Yes
Input
CMOS, LVDS, LVPECL
Output
CMOS, LVDS
Number Of Circuits
1
Ratio - Input:output
2:12, 2:24
Differential - Input:output
Yes/Yes
Frequency - Max
2.95GHz
Divider/multiplier
Yes/No
Voltage - Supply
3.135 V ~ 3.465 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
64-LFCSP
Frequency-max
2.8GHz
Operating Temperature (min)
-40C
Operating Temperature Classification
Industrial
Operating Temperature (max)
85C
Rad Hardened
No
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AD9522-0BCPZ
Manufacturer:
Analog Devices Inc
Quantity:
135
Company:
Part Number:
AD9522-0BCPZ
Manufacturer:
AD
Quantity:
25
Part Number:
AD9522-0BCPZ
Manufacturer:
ADI/亚德诺
Quantity:
20 000
Reg.
Addr
(Hex) Bit(s) Name
01F
01F
01F
AD9522-0
Table 53. Output Driver Control
Reg.
Addr
(Hex) Bit(s) Name
0F0
0F0
0F0
0F0
0F0
0F1
0F2
0F3
0F4
0F5
[2]
[1]
[0]
[7]
[6:5]
[4:3]
[2:1]
[0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
REF2 frequency
> threshold
(read-only)
REF1 frequency
> threshold
(read-only)
Digital lock
detect
(read-only)
OUT0 format
OUT0 CMOS
configuration
OUT0 polarity
OUT0 LVDS
differential
voltage
OUT0 LVDS
power-down
OUT1 control
OUT2 control
OUT3 control
OUT4 control
OUT5 control
Description
Readback register. Indicates if the frequency of the signal at REF2 is greater than the threshold frequency
set by Register 0x01A[6].
[2] = 0; REF2 frequency is less than the threshold frequency.
[2] = 1; REF2 frequency is greater than the threshold frequency.
Readback register. Indicates if the frequency of the signal at REF1 is greater than the threshold frequency
set by Register 0x01A[6].
[1] = 0; REF1 frequency is less than the threshold frequency.
[1] = 1; REF1 frequency is greater than the threshold frequency.
Readback register. Digital lock detect.
[0] = 0; PLL is not locked.
[0] = 1; PLL is locked.
Description
Selects the output type for OUT0.
[7] = 0; LVDS (default).
[7] = 1; CMOS.
Sets the CMOS output configuration for OUT0 when 0x0F0[7] = 1.
[6:5]
00
01
10
11 (default)
Sets the output polarity for OUT0.
[7]
0 (default)
0
1
1
1
1
Sets the LVDS output differential voltage (V
[2]
0
0 (default)
1
1
LVDS power-down.
[0] = 0; normal operation (default).
[0] = 1; power-down. Output driver is in a high impedance state.
This register controls OUT1, and the bit assignments for this register are identical to Register 0x0F0.
This register controls OUT2, and the bit assignments for this register are identical to Register 0x0F0.
This register controls OUT3, and the bit assignments for this register are identical to Register 0x0F0.
This register controls OUT4, and the bit assignments for this register are identical to Register 0x0F0.
This register controls OUT5, and the bit assignments for this register are identical to Register 0x0F0.
OUT0A
Tristate
On
Tristate
On
[4]
X
X
0 (default)
0
1
1
[1]
0
1 (default)
0
1
Rev. 0 | Page 74 of 84
Tristate
On
0
1
0 (default)
0
1
OUT0B
Tristate
On
[3]
1
I
1.75 (V
3.5 (V
5.25 (V
7.0 (V
OD
(mA)
OD
OD
OD
OD
= 350 mV for 100 Ω termination across differential pair)
= 700 mV for 100 Ω termination across differential pair)
= 175 mV for 100 Ω termination across differential pair)
= 525 mV for 100 Ω termination across differential pair)
OD
).
Output Type
LVDS
LVDS
CMOS
CMOS
CMOS
CMOS
OUT0A
Noninverting
Inverting
Noninverting
Inverting
Noninverting
Inverting
OUT0B
Inverting
Noninverting
Noninverting
Inverting
Inverting
Noninverting