AD9522-5BCPZ-REEL7 Analog Devices Inc, AD9522-5BCPZ-REEL7 Datasheet - Page 21
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AD9522-5BCPZ-REEL7
Manufacturer Part Number
AD9522-5BCPZ-REEL7
Description
12- Channel Clock Generator With Integra
Manufacturer
Analog Devices Inc
Type
Clock Generator, Fanout Distributionr
Datasheet
1.AD9522-5BCPZ-REEL7.pdf
(76 pages)
Specifications of AD9522-5BCPZ-REEL7
Pll
Yes
Input
CMOS, LVDS, LVPECL
Output
CMOS, LVDS, LVPECL
Number Of Circuits
1
Ratio - Input:output
2:12, 2:24
Differential - Input:output
Yes/Yes
Frequency - Max
2.4GHz
Divider/multiplier
Yes/No
Voltage - Supply
3.135 V ~ 3.465 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
64-LFCSP
Frequency-max
800MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Figure 18. CMOS Output Swing vs. Frequency and Capacitive Load
–100
–110
–120
–130
–140
–150
–160
–100
–110
–120
–130
–140
–150
–160
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
10
10
0
Figure 19. Additive (Residual) Phase Noise,
Figure 20. Additive (Residual) Phase Noise,
100
100
100
CLK-to-LVDS @ 245.76 MHz, Divide-by-1
CLK-to-LVDS @ 200 MHz, Divide-by-5
200
1k
1k
FREQUENCY (MHz)
FREQUENCY (Hz)
FREQUENCY (Hz)
10k
10k
300
100k
100k
400
500
1M
1M
10M
10M
600
2pF
10pF
20pF
100M
100M
7
00
Rev. 0 | Page 21 of 76
–100
–110
–120
–130
–140
–150
–110
–120
–130
–140
–150
–160
–170
–100
–110
–120
–130
–140
–150
–160
10
10
10
Figure 21. Additive (Residual) Phase Noise,
Figure 22. Additive (Residual) Phase Noise,
Figure 23. Additive (Residual) Phase Noise,
100
100
100
CLK-to-CMOS @ 50 MHz, Divide-by-20
CLK-to-CMOS @ 250 MHz, Divide-by-4
CLK-to-LVDS @ 800 MHz, Divide-by-1
1k
1k
1k
FREQUENCY (Hz)
FREQUENCY (Hz)
FREQUENCY (Hz)
10k
10k
10k
100k
100k
100k
1M
1M
1M
AD9522-5
10M
10M
10M
100M
100M
100M