AD9523-1/PCBZ Analog Devices Inc, AD9523-1/PCBZ Datasheet
AD9523-1/PCBZ
Specifications of AD9523-1/PCBZ
Related parts for AD9523-1/PCBZ
AD9523-1/PCBZ Summary of contents
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... PLL and VCO with two VCO dividers. The on-chip VCO tunes from 2.94 GHz to 3.1 GHz. The AD9523-1 is defined to support the clock requirements for long term evolution (LTE) and multicarrier GSM base station designs. It relies on an external VCXO to provide the reference jitter cleanup to achieve the restrictive low phase noise require- ments necessary for acceptable data converter SNR performance ...
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... AD9523-1 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Conditions ..................................................................................... 3 Supply Current.............................................................................. 3 Power Dissipation......................................................................... 5 REFA, REFA , REFB, REFB , OSC_IN, OSC_IN , and ZD_IN, ZD_IN Input Characteristics ...................................................... 6 OSC_CTRL Output Characteristics .......................................... 6 REF_TEST Input Characteristics ............................................... 6 PLL1 Output Characteristics ...................................................... 7 OUT0, OUT0 to OUT13, OUT13 Distribution Output Characteristics ...
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... Use VCO Divider M2; values are independent of the number of outputs turned on mA Current for each divider 122.88 MHz mA Current for each divider 983.04 MHz Channel x control register, Bit 122.88 MHz 983.04 MHz 122.88 MHz 983.04 MHz 122.88 MHz 983.04 MHz AD9523-1 ...
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... AD9523-1 Parameter HSTL Mode VDD3_OUT[x:y], Supply Voltage Clock Output Drivers 1 VDD3_OUT[x:y], Supply Voltage Clock Output Drivers HSTL Mode VDD3_OUT[x:y], 1 Supply Voltage Clock Output Drivers 1 VDD3_OUT[x:y], Supply Voltage Clock Output Drivers CMOS Mode (Single-Ended) 1 VDD3_OUT[x:y], Supply Voltage Clock Output Drivers CLOCK OUTPUT DRIVERS—LOWER POWER MODE ON ...
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... Single 8 mA HSTL output at 122.88 MHz 94 108.1 mW Single 8 mA HSTL output at 983.04 MHz 48 55.2 mW Single 16 mA HSTL output at 122.88 MHz 153 176 mW Single 16 mA HSTL output at 983.04 MHz Rev Page AD9523-1 = 122.88 MHz 2949.12 MHz, VCO Divider M1 VCO = 2949.12 MHz, VCO Divider VCO VCO ...
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... AD9523-1 REFA, REFA, REFB, REFB, OSC_IN, OSC_IN, AND ZD_IN, ZD_IN INPUT CHARACTERISTICS Table 4. Parameter Min DIFFERENTIAL MODE Input Frequency Range Input Slew Rate (OSC_IN) 400 Common-Mode Internally 0.6 Generated Input Voltage Input Common-Mode Range 1.025 Differential Input Voltage, 100 Sensitivity Frequency < 250 MHz ...
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... MHz to 1 GHz 454 mV Voltage swing between output pins; output driver static 50 mV Absolute difference between voltage swing of normal pin and inverted pin 1.375 V Output driver static 50 mV Voltage difference between output pins; output driver static 3 Output driver static Rev Page AD9523-1 /ΔVDD3) OD ...
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... AD9523-1 Parameter Min CMOS MODE Maximum Output Frequency Rise Time/Fall Time (20% to 80%) Duty Cycle 45 Output Voltage High VDD − 0.25 VDD − 0.1 Output Voltage Low TIMING ALIGNMENT CHARACTERISTICS Table 9. Parameter Min OUTPUT TIMING SKEW Between Outputs in Same Group 1 LVPECL, HSTL, and LVDS ...
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... MHz 125 MHz Min Typ Max Unit Test Conditions/Comments 2.0 V 0.8 V ±80 ±250 μA The minus sign indicates that, due to the internal pull-up resistor, current is flowing out of the AD9523 100 ns 1.5 ns High speed clock is the CLK input signal Rev Page AD9523-1 ...
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... V 25 MHz 3 Rev Page Test Conditions/Comments Test Conditions/Comments CS has an internal 40 kΩ pull-up resistor The minus sign indicates that, due to the internal pull-up resistor, current is flowing out of the AD9523-1 SCLK has an internal 40 kΩ pull-down resistor in SPI mode but not mode ...
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... C 300 0 300 B 100 100 880 400 C master must also provide a minimum hold time of 300 ns for the SDA signal to bridge the undefined region of the SCL Rev Page AD9523-1 Unit Test Conditions/Comments V V μ Note that all I C timing values are referred to VIH (0.3 × ...
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... AD9523-1 ABSOLUTE MAXIMUM RATINGS Table 16. Parameter VDD3_PLL, VDD3_REF, VDD3_OUT[x:y], LDO_VCO to GND REFA, REFA, REFB, REFB to GND SCLK/SCL, SDIO/SDA, SDO GND OUT0, OUT0, OUT1, OUT1, OUT2, OUT2, OUT3, OUT3, OUT4, OUT4, OUT5, OUT5, OUT6, OUT6, OUT7, OUT7, OUT8, OUT8, OUT9, OUT9, OUT10, OUT10, OUT11, ...
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... Complementary PLL1 Oscillator Input. Along with OSC_IN, this pin is the differential input for the PLL reference. Alternatively, this pin can be programmed as a single-ended 3.3 V CMOS input. 1 PIN 1 2 INDICATOR AD9523 TOP VIEW 10 (Not to Scale Figure 2. Pin Configuration Rev Page AD9523-1 54 VDD1.8_OUT[4:5] 53 OUT4 52 OUT4 51 VDD3_OUT[4:5] 50 OUT5 49 OUT5 48 VDD1.8_OUT[6:7] 47 OUT6 46 OUT6 45 VDD3_OUT[6:7] 44 OUT7 43 OUT7 42 VDD1.8_OUT[8:9] ...
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... AD9523-1 Pin 1 No. Mnemonic Type Description 11 LF2_EXT_CAP O PLL2 External Loop Filter Capacitor Connection. Connect capacitor to this pin and the LDO_VCO pin. 12 LDO_VCO P/O 2.5 V LDO Internal Regulator Decoupling Pin for VCO. Connect a 0.47 μF decoupling capacitor from this pin to ground. Note that, for best performance, the LDO bypass capacitor must be placed in close proximity to the device ...
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... EEPROM Select. Setting this pin high selects the register values stored in the internal EEPROM to be loaded at reset and/or power-up. Setting this pin low causes the AD9523-1 to load the hard-coded default register values at power-up/reset. This pin has an internal 40 kΩ pull-down resistor. ...
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... AD9523-1 TYPICAL PERFORMANCE CHARACTERISTICS f = 122.88 MHz, REFA differential at 30.72 MHz, f VCXO 60 50 HSTL = 16mA 40 30 HSTL = 8mA 200 400 600 FREQUENCY (MHz) Figure 3. VDD3_OUT[x:y] Current (Typical) vs. Frequency; HSTL Mode and LVDS = 7mA 200 400 600 FREQUENCY (MHz) Figure 4. VDD3_OUT[x:y] Current (Typical) vs. Frequency; ...
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... Figure 11. Output Waveform (Differential), LVPECL at 122.88 MHz 1 1000 1200 CH1 500mV Ω Figure 12. Output Waveform (Differential), HSTL at 16 mA, 122.88 MHz Rev Page AD9523-1 2pF 10pF 20pF 100 200 300 400 500 FREQUENCY (MHz) CMOS Mode at 2 pF, 10 pF, and 20 pF Load 2 ...
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... AD9523-1 –80 –90 –100 –110 –120 1 –130 2 –140 3 –150 NOISE: ANALYSIS RANGE x: START 10kHz TO STOP 40MHz –160 INTG NOISE: –78.1dBc/40MHz RMS NOISE: 175.4µRAD 10.0mdeg –170 RMS JITTER: 151.4fsec RESIDUAL FM: 2.1kHz –180 100 1k 10k 100k FREQUENCY (Hz) Figure 13. Phase Noise, Output = 184.32 MHz (VCXO = 122.88 MHz, Crystek VCXO CVHD-950) ...
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... Figure 19. AC-Coupled LVPECL Output Driver AD9523-1 LVPECL- HIGH COMPATIBLE 100Ω IMPEDANCE OUTPUT INPUT Figure 20. DC-Coupled LVPECL Output Driver AD9523-1 DOWNSTREAM DEVICE AD9523-1 DOWNSTREAM DEVICE DOWNSTREAM DEVICE Figure 23. REFx, VCXO, and Zero Delay Input Differential Mode DOWNSTREAM DEVICE Rev Page 0.1µF HIGH HSTL DOWNSTREAM IMPEDANCE 100Ω ...
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... AD9523-1 TERMINOLOGY Phase Jitter and Phase Noise An ideal sine wave can be thought of as having a continuous and even progression of phase with time from 0° to 360° for each cycle. Actual signals, however, display a certain amount of variation from ideal phase progression over time. This phenomenon is called phase jitter ...
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... Figure 24. Top Level Diagram A register setting determines what action to take if the failed reference is once again available: either stay on Reference B or revert to Reference A. If neither reference is usable, the AD9523-1 supports a holdover mode. A reference select pin (REF_SEL, Pin 16) is available to manually select which input reference is active (see Table 42) ...
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... VCXO operating in a closed loop (see Figure 26). PLL1 has the flexibility to operate with a loop bandwidth of approximately 100 Hz. This relatively narrow loop bandwidth gives the AD9523-1 the ability to suppress jitter that appears on the input references (REFA and REFB). The output of PLL1 then becomes a low jitter phase-locked version of the reference input system clock ...
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... REFA and REFB signals (that is, after division by the input dividers). The status of the reference monitor guides the activity of the switchover control logic. The AD9523-1 supports automatic and manual PLL reference clock switching between REFA (the REFA and REFA pins) and REFB (the REFB and REFB pins) ...
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... The VCO dividers provide frequency division between the internal VCO and the clock distribution. Each VCO divider can be set to divide When the AD9523-1 is used without any zero delay feedback (internal or external), the phase relationship between the reference inputs and the outputs is a function of the phase relationship between the OSC input and the reference inputs ...
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... VCO Divider M1 or VCO Divider M2, selectable via the register settings. The distribution output consists of 14 channels (OUT0 to OUT13). Each of the output channels has a dedicated divider and output driver, as shown in Figure 29. The AD9523-1 also has the capability to route the VCXO output to four of the outputs (OUT0 to OUT3). ...
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... SYNC pin or the sync dividers bit (Register 0x232, Bit 0). DIVIDE PHASE SYNC FAN OUT SYNC Figure 29. Clock Distribution Synchronization Block Diagram 6 × 0.5 PERIODS Figure 30. Clock Output Synchronization Timing Diagram Rev Page port before the AD9523-1 OUTx DRIVER OUT DIVIDER OUTx ...
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... PLL1 to maximum gives the best zero delay matching. Internal Zero Delay Mode The internal zero delay function of the AD9523-1 is achieved by feeding the output of Channel Divider 0 back to the PLL1 N divider. Bit 5 in Register 0x01B is used to select internal zero delay mode (see Table 41) ...
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... The AD9523-1 supports both I2C protocols: standard mode (100 kHz) and fast mode (400 kHz). The AD9523-1 I2C port has a 2-wire interface consisting of a serial data line (SDA) and a serial clock line (SCL I2C bus system, the AD9523-1 is connected to the serial bus (data bus SDA and clock bus SCL slave device, meaning that no clock is generated by the AD9523-1 ...
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... Data ACKNOWLEDGE FROM SLAVE-RECEIVER Figure 34. Acknowledge Bit ACKNOWLEDGE FROM SLAVE-RECEIVER ACKNOWLEDGE FROM MASTER-RECEIVER Rev Page AD9523 transfer can contain multiple data ACKNOWLEDGE FROM SLAVE-RECEIVER ACKNOWLEDGE FROM SLAVE-RECEIVER ACKNOWLEDGE FROM SLAVE-RECEIVER − ...
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... AD9523-1 A repeated start (Sr) condition can be used in place of a stop condition. Furthermore, a start or stop condition can occur at any time; partially transferred bytes are discarded. 2 For data write transfer containing multiple data bytes, the peripheral drives a no acknowledge for the data byte that Data Transfer Format Send byte format ...
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... SDO). By default, the AD9523 bidirectional mode. Short instruction mode (8-bit instructions) is not supported. Only long (16-bit) instruction mode is supported. A write or a read operation to the AD9523-1 is initiated by pulling CS low. The CS stalled high mode is supported in data transfers where three or fewer bytes of data (plus instruction data) are transferred ...
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... Only Bits[A11:A0] are needed to cover the range of the 0x234 registers used by the AD9523-1. Bit A12 must always be 0. For multibyte transfers, this address is the starting byte address. In MSB first mode, subsequent bytes decrement the address ...
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... CLK t LOW A12 A11 A10 DATA BIT N DATA BIT N – 1 Figure 43. Timing Diagram for Serial Control Port Register Read REGISTER (N) DATA Rev Page AD9523 REGISTER (N – 1) DATA REGISTER (N – 2) DATA REGISTER (N – 3) DATA REGISTER ( DATA DON'T CARE DON'T CARE DON'T CARE ...
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... AD9523 SCLK SDIO BIT N Table 27. Serial Control Port Timing Parameter Description t Setup time between data and rising edge of SCLK DS t Hold time between data and rising edge of SCLK DH t Period of the clock CLK t Setup time between the CS falling edge and SCLK rising edge (start of communication cycle) ...
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... SPI mode, users can read the value of the Status_EEPROM bit (1 = data transfer in process and 0 = data transfer complete). In I2C mode, the user can address the AD9523-1 slave port with the external I2C master (send an address byte to the AD9523-1). If the AD9523-1 responds with a no acknowledge bit, the data transfer was not received ...
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... This is needed so that at least one IO_Update occurs after all of the AD9523-1 registers are loaded when the EEPROM is read. If this operational code is absent during a write to the EEPROM, the register values loaded from the EEPROM are not transferred to the active register space, and these values do not take effect after they are loaded from the EEPROM to the AD9523-1 ...
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... Address of the second group of registers (Bits[7:0]) Number of bytes of the third group of registers (Bits[6:0]) Address of the third group of registers (Bits[15:8]) Address of the third group of registers (Bits[7:0]) IO_Update operational code (0x80) End-of-data operational code (0xFF) Rev Page AD9523-1 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) ...
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... Output clock speed • Supply voltage • Ambient temperature The combination of these variables determines the junction temperature within the AD9523-1 device for a given set of operating conditions. The AD9523-1 is specified for an ambient temperature (T ensure that T is not exceeded, an airflow source can be used. A ...
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... Example 2. THERMALLY ENHANCED PACKAGE MOUNTING GUIDELINES = 20.1 was used. °C/W Refer to the Manufacturing Guide for the Lead Frame Chip Scale Package (LFCSP), for more information about mounting devices with an exposed paddle. Rev Page AD9523-1 AN-772 Application Note, A Design and ...
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... AD9523-1 CONTROL REGISTERS CONTROL REGISTER MAP Register addresses that are not listed in Table 30 are not used, and writing to those registers has no effect. Registers that are marked as reserved should never have their values changed. When writing to registers with bits that are marked reserved, the user should take care to always write the default value for the reserved bits ...
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... Driver mode 10-bit channel divider[9:8] (MSB) Driver mode 10-bit channel divider[9:8] (MSB) Driver mode 10-bit channel divider[9:8] (MSB) Driver mode 10-bit channel divider[9:8] (MSB) Driver mode 10-bit channel divider[9:8] (MSB) AD9523-1 Default Value (Hex) 0x00 0x00 0x04 0x03 0x00 0x00 0x00 ...
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... AD9523-1 Addr Register (MSB) (Hex) Name Bit 7 Bit 6 0x1A2 Channel 6 Invert Ignore control divider sync output 0x1A3 0x1A4 0x1A5 Channel 7 Invert Ignore control divider sync output 0x1A6 0x1A7 0x1A8 Channel 8 Invert Ignore control divider sync output 0x1A9 0x1AA 0x1AB Channel 9 Invert ...
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... High byte of register address (clock input and REF segment) Low byte of register address (clock input and REF segment) Instruction (data)[7:0] (other segment) High byte of register address (other segment) Low byte of register address (other segment) I/O update Rev Page AD9523-1 (LSB) Bit 2 Bit 1 Bit 0 STATUS0 Reserved ...
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... AD9523-1 Addr Register (MSB) (Hex) Name Bit 7 Bit 6 0xA16 EEPROM Buffer Segment Register 23 EEPROM Control 0xB00 Status_ Reserved Reserved EEPROM (read only) 0xB01 EEPROM error Reserved Reserved checking readback (read only) 0xB02 EEPROM Reserved Reserved Control 1 0xB03 EEPROM Reserved Reserved Control 2 ...
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... EEPROM 16-bit EEPROM ID, Bits[7:0]. This register, along with Register 0x006, allows the user to store a unique customer ID to identify which version of the AD9523-1 register settings is stored in the EEPROM. It does not version ID (LSB) affect AD9523-1 operation in any way (default: 0x00). 0x006 [7:0] EEPROM 16-bit EEPROM ID, Bits[15:8] ...
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... AD9523-1 Input PLL (PLL1) (Address 0x010 to Address 0x01D) Table 34. PLL1 REFA R Divider Control Address Bits Bit Name 0x010 [7:0] REFA R divider 0x011 [1:0] Table 35. PLL1 REFB R Divider Control Address Bits Bit Name 0x012 [7:0] REFB R divider 0x013 [1:0] 1 Requires Register 0x01C, Bit for division that is independent of REFA division. ...
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... Selects which single-ended input pin is enabled when in single-ended receiver mode (Register 0x01A, Bit 6 = 0). 1: REFB pin enabled. 0: REFB pin enabled. Selects which single-ended input pin is enabled when in single-ended receiver mode (Register 0x01A, Bit 5 = 0). 1: REFA pin enabled. 0: REFA pin enabled. Rev Page AD9523-1 ...
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... AD9523-1 Table 42. PLL1 Miscellaneous Control Address Bits Bit Name 0x01C 7 Enable REFB R divider independent division control 6 OSC_CTRL control voltage to VCC/2 when reference clock fails 5 Reserved [4:2] Reference selection mode 1 Bypass REFB R divider 0 Bypass REFA R divider don’t care. Table 43. PLL1 Loop Filter Zero Resistor Control ...
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... PLL1 does not consider valid. Selects VCO control voltage functionality. 0 (default): normal VCO operation. 1: forces VCO control voltage to midscale. 1: initiates VCO calibration (this is not an autoclearing bit). 0: resets the VCO calibration. Reserved. Rev Page AD9523-1 Allowed N Division (4 × 16, 17 20, 21, 22 24, 25, 26 28, 29 … continuous to 255 ...
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... AD9523-1 Table 48. VCO Divider Control Address Bits Bit Name 0x0F4 7 Reserved 6 VCO Divider M2 power-down [5:4] VCO Divider M2 3 Reserved 2 VCO Divider M1 power-down [1:0] VCO Divider M1 Table 49. PLL2 Loop Filter Control Address Bits Bit Name 0x0F5 [7:6] Pole 2 resistor (R POLE2 [5:3] Zero resistor (R ...
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... CMOS (both outputs out of phase) + Pin: complement phase relative to divider output − Pin: true phase relative to divider output CMOS + Pin: complement phase relative to divider output − Pin: high CMOS + Pin: high-Z − Pin: complement phase relative to divider output Tristate output Rev Page AD9523-1 ...
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... AD9523-1 Address Bits Bit Name 0x191 [7:0] Channel divider, Bits[7:0] (LSB) 0x192 [7:2] Divider phase [1:0] Channel divider, Bits[9:8] (MSB) Table 52. PLL1 Output Control (PLL1_OUT, Pin 72) Address Bits Bit Name 0x1BA [7:5] CLK2 select[2:0] 4 PLL1 output CMOS driver strength [3:0] PLL1 output divider Table 53 ...
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... Reserved. 1: holdover is active (both references are missing). 0: normal operation. Selected reference (applies only when the device automatically selects the reference; for example, not in manual control mode). 1: REFB. 0: REFA. Reserved. 1: VCO calibration in progress. 0: VCO calibration not in progress. Rev Page AD9523-1 ...
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... AD9523-1 Other (Address 0x230 to Address 0x234) Table 55. Status Signals Address Bits Bit Name 0x230 [7:6] Reserved [5:0] Status Monitor 0 control Description Reserved. Bit 5 Bit 4 Bit 3 Bit 2 Bit Note that all bit combinations after 010111 are reserved. Rev Page Bit 0 Muxout 0 GND ...
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... Register 0x230, Bits[5:0] are in the range of 000000 to 001111. 1: enable. 0: disable. Reserved. Set bit to put dividers in sync; clear bit to release. Functions like SYNC pin low. 1: sync. 0: normal. Rev Page AD9523-1 Bit 0 Muxout 0 GND 1 PLL1 and PLL2 locked 0 ...
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... AD9523-1 Table 56. Power-Down Control Address Bits Bit Name 0x233 [7:3] Reserved 2 PLL1 power-down 1 PLL2 power-down 0 Distribution power-down Table 57. Update All Registers Address Bits Bit Name 0x234 [7:1] Reserved 0 IO_Update EEPROM Buffer (Address 0xA00 to Address 0xA16) Table 58. EEPROM Buffer Segment Address Bits ...
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... REG2EEPROM Description Reserved. When the EEPROM_SEL pin is tied low, setting the Soft_EEPROM bit resets the AD9523-1 using the settings saved in EEPROM. 1: soft reset with EEPROM settings (self-clearing). Enables the user to write to the EEPROM. 0: EEPROM write protection is enabled. User cannot write to EEPROM (default). ...
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... SEATING PLANE 0.23 0.18 ORDERING GUIDE 1 Model Temperature Range AD9523-1BCPZ −40°C to +85°C AD9523-1BCPZ-REEL7 −40°C to +85°C AD9523-1/PCBZ RoHS Compliant Part. 0.60 0.42 0.24 0.50 9.75 BSC BSC SQ 0.50 0.40 0.30 0.80 MAX 0.65 TYP 0.05 MAX ...
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... NOTES Rev Page AD9523-1 ...
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... AD9523-1 NOTES refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). ©2010–2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09278-0-3/11(B) Rev Page ...