AD9601-250EBZ Analog Devices Inc, AD9601-250EBZ Datasheet - Page 9

• Manufacturer Part Number: AD9601-250EBZ
• Description: 10-Bit 250 Msps LowPwr CMOS ADC
• Manufacturer: Analog Devices Inc

Specifications of AD9601-250EBZ

• Number Of Adc's: 1
• Number Of Bits: 10
• Sampling Rate (per Second): 250M
• Data Interface: Serial
• Inputs Per Adc: 1 Differential
• Input Range: 1.25 Vpp
• Power (typ) @ Conditions: 322mW @ 250MSPS
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: AD9601-250
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9601-250EBZ - BOARD EVALUATION AD9601-250
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Table 7. Single Data Rate Mode Pin Function Descriptions
Pin No.
30, 32, 33, 34, 37, 38, 39,
41, 42, 43, 46
7, 24, 47
0
8, 23, 48
35
36
40
44
45
31
28
25
26
27
29
49
50
53
54
55
56
1
2
3
Mnemonic
AVDD
DRVDD
AGND
DRGND
VIN+
VIN−
CML
CLK+
CLK−
RBIAS
RESET
SDIO/DCS
SCLK/DFS
CSB
PWDN
DCO−
DCO+
DA0 (LSB)
DA1
DA2
DA3
DA4
DA5
DA6
1
1
(MSB) DA9
(LSB) DB0
DRGND
DRVDD
OVRA
DA4
DA5
DA6
DA7
DA8
DB1
DB2
NIC
NIC
Description
1.8 V Analog Supply.
1.8 V Digital Output Supply.
Analog Ground.
Digital Output Ground.
Analog Input—True.
Analog Input—Complement.
Common-Mode Output Pin. Enabled through the SPI, this pin provides a reference for the
optimized internal bias voltage for VIN+/VIN−.
Clock Input—True.
Clock Input—Complement.
Set Pin for Chip Bias Current. (Place 1% 10 kΩ resistor terminated to ground.)
Nominally 0.5 V.
CMOS-Compatible Chip Reset (Active Low).
Serial Port Interface (SPI) Data Input/Output (Serial Port Mode); Duty Cycle Stabilizer
Select (External Pin Mode).
Serial Port Interface Clock (Serial Port Mode); Data Format Select Pin (External Pin Mode).
Serial Port Chip Select (Active Low).
Chip Power-Down.
Data Clock Output—Complement.
Data Clock Output—True.
Output Port A Output Bit 0 (LSB).
Output Port A Output Bit 1.
Output Port A Output Bit 2.
Output Port A Output Bit 3.
Output Port A Output Bit 4.
Output Port A Output Bit 5.
Output Port A Output Bit 6.
10
11
12
13
14
1
2
4
5
6
7
8
9
3
PIN 0 (EXPOSED PADDLE) = AGND
Figure 4. Pin Configuration
PIN 1
INDICATOR
Rev. 0 | Page 9 of 32
(Not to Scale)
AD9601
TOP VIEW
42 AVDD
41 AVDD
40 CML
39 AVDD
38 AVDD
37 AVDD
36 VIN–
35 VIN+
34 AVDD
33 AVDD
32 AVDD
31 RBIAS
30 AVDD
29 PWDN
AD9601