AD9609-20EBZ Analog Devices Inc, AD9609-20EBZ Datasheet - Page 26

• Manufacturer Part Number: AD9609-20EBZ
• Description: 10 Bit 20 Msps Low Pwr ADC
• Manufacturer: Analog Devices Inc

Specifications of AD9609-20EBZ

• Number Of Adc's: 1
• Number Of Bits: 10
• Sampling Rate (per Second): 20M
• Data Interface: Serial, SPI™
• Inputs Per Adc: 1 Differential
• Input Range: 2 Vpp
• Power (typ) @ Conditions: 46.3mW @ 20MSPS
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: AD9609
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9609
HARDWARE INTERFACE
The pins described in Table 14 constitute the physical interface
between the programming device of the user and the serial port
of the AD9609. The SCLK pin and the CSB pin function as inputs
when using the SPI interface. The SDIO pin is bidirectional,
functioning as an input during write phases and as an output
during readback.
The SPI interface is flexible enough to be controlled by
either FPGAs or microcontrollers. One method for SPI
configuration is described in detail in the AN-812 Appli-
cation Note, Microcontroller-Based Serial Port Interface
(SPI) Boot Circuit.
The SPI port should not be active during periods when the full
dynamic performance of the converter is required. Because the
SCLK signal, the CSB signal, and the SDIO signal are typically
asynchronous to the ADC clock, noise from these signals can
degrade converter performance. If the on-board SPI bus is used for
other devices, it may be necessary to provide buffers between
this bus and the AD9609 to prevent these signals from transi-
tioning at the converter inputs during critical sampling periods.
SDIO/PDWN and SCLK/DFS serve a dual function when the
SPI interface is not being used. When the pins are strapped to
DRVDD or ground during device power-on, they are associated
with a specific function. The Digital Outputs section describes
the strappable functions supported on the AD9609.
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CONFIGURATION WITHOUT THE SPI
In applications that do not interface to the SPI control registers,
the SDIO/PDWN pin and the SCLK/DFS pin serve as standalone
CMOS-compatible control pins. When the device is powered up, it
is assumed that the user intends to use the pins as static control
lines for the power-down and output data format feature control.
In this mode, connect the CSB chip select to DRVDD, which
disables the serial port interface.
Table 15. Mode Selection
Pin
SDIO/PDWN
SCLK/DFS
SPI ACCESSIBLE FEATURES
Table 16 provides a brief description of the general features that
are accessible via the SPI. These features are described in detail
in the AN-877 Application Note, Interfacing to High Speed ADCs
via SPI. The AD9609 part-specific features are described in
detail in Table 17.
Table 16. Features Accessible Using the SPI
Feature
Modes
Clock
Offset
Test I/O
Output Mode
Output Phase
Output Delay
VREF
External
Voltage
DRVDD
AGND (default)
DRVDD
AGND (default)
Allows the user to vary the DCO delay
Description
Allows the user to set either power-down mode
or standby mode
Allows the user to access the DCS via the SPI
Allows the user to digitally adjust the
converter offset
Allows the user to set test modes to have known
data on output bits
Allows the user to set up outputs
Allows the user to set the output clock polarity
Allows the user to set the reference voltage
Configuration
Chip power-down mode
Normal operation (default)
Twos complement enabled
Offset binary enabled