AD9627BCPZ-80 Analog Devices Inc, AD9627BCPZ-80 Datasheet - Page 5

• Manufacturer Part Number: AD9627BCPZ-80
• Description: IC,A/D CONVERTER,DUAL,12-BIT,LLCC,64PIN
• Manufacturer: Analog Devices Inc

Specifications of AD9627BCPZ-80

• Number Of Bits: 12
• Sampling Rate (per Second): 80M
• Data Interface: Serial, SPI™
• Number Of Converters: 2
• Power Dissipation (max): 490mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9627-150EBZ - BOARD EVAL FOR AD9627-150AD9627-125EBZ - IC A/D 12BIT 125MSPS DL EVAL BRD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SPECIFICATIONS
ADC DC SPECIFICATIONS—AD9627-80/AD9627-105
AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 3.3 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, DCS
enabled, fast detect output pins disabled, and signal monitor disabled, unless otherwise noted.
Table 1.
Parameter
RESOLUTION
ACCURACY
MATCHING CHARACTERISTIC
TEMPERATURE DRIFT
INTERNAL VOLTAGE REFERENCE
INPUT REFERRED NOISE
ANALOG INPUT
VREF INPUT RESISTANCE
POWER SUPPLIES
POWER CONSUMPTION
1
2
3
4
Measured with a low input frequency, full-scale sine wave, with approximately 5 pF loading on each output bit.
Input capacitance refers to the effective capacitance between one differential input pin and AGND. See Figure 8 for the equivalent analog input structure.
The maximum limit applies to the combination of I
Standby power is measured with a dc input and with the CLK pins inactive (set to AVDD or AGND).
No Missing Codes
Offset Error
Gain Error
Differential Nonlinearity (DNL)
Integral Nonlinearity (INL)
Offset Error
Gain Error
Offset Error
Gain Error
Output Voltage Error (1 V Mode)
Load Regulation @ 1.0 mA
VREF = 1.0 V
Input Span, VREF = 1.0 V
Input Capacitance
Supply Voltage
Supply Current
DC Input
Sine Wave Input
Sine Wave Input
Standby Power
Power-Down Power
AVDD, DVDD
DRVDD (CMOS Mode)
DRVDD (LVDS Mode)
I
I
I
I
I
AVDD
DVDD
DRVDD
DRVDD
DRVDD
1, 3
1, 3
1
1
1
(3.3 V CMOS)
(1.8 V CMOS)
(1.8 V LVDS)
4
1
1
(DRVDD = 1.8 V)
(DRVDD = 3.3 V)
2
1
1
Temperature
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
25°C
Full
25°C
Full
Full
Full
25°C
Full
Full
Full
Full
Full
Full
Full
Full
Full
AVDD
and I
DVDD
currents.
Min
12
+0.1
1.7
1.7
1.7
Rev. B | Page 5 of 76
AD9627-80
Guaranteed
Typ
±0.2
−1.8
±0.2
±0.4
±0.2
±0.2
±15
±95
±5
7
0.3
2
8
6
1.8
3.3
1.8
233
26
23
11
47
452
495
550
52
2.5
Max
±0.6
−3.7
±0.4
±0.9
±0.6
±0.75
±16
1.9
3.6
1.9
278
490
6
Min
12
−0.5
1.7
1.7
1.7
AD9627-105
Guaranteed
Typ
±0.3
−2.2
±0.2
±0.4
±0.3
±0.2
±15
±95
±5
7
0.3
2
8
6
1.8
3.3
1.8
310
34
34
15
47
600
657
740
68
2.5
Max
±0.7
−3.7
±0.4
±0.9
±0.7
±0.75
±16
1.9
3.6
1.9
365
650
6
Unit
Bits
% FSR
% FSR
LSB
LSB
LSB
LSB
% FSR
% FSR
ppm/°C
ppm/°C
mV
mV
LSB rms
V p-p
pF
kΩ
V
V
V
mA
mA
mA
mA
mA
mW
mW
mW
mW
mW
AD9627