AD9627BCPZ11-150 Analog Devices Inc, AD9627BCPZ11-150 Datasheet - Page 32

• Manufacturer Part Number: AD9627BCPZ11-150
• Description: IC,A/D CONVERTER,DUAL,11-BIT,LLCC,64PIN
• Manufacturer: Analog Devices Inc

Specifications of AD9627BCPZ11-150

• Number Of Bits: 11
• Sampling Rate (per Second): 150M
• Data Interface: Serial, SPI™
• Number Of Converters: 2
• Power Dissipation (max): 890mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9627-150EBZ - BOARD EVAL FOR AD9627-150AD9627-125EBZ - IC A/D 12BIT 125MSPS DL EVAL BRD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9627-11
Increment Gain (IG) and Decrement Gain (DG)
The increment gain and decrement gain indicators are intended
to be used together to provide information to enable external
gain control. The decrement gain indicator works in
conjunction with the coarse upper threshold bits, asserting when
the input magnitude is greater than the 3-bit value in the coarse
upper threshold register (Address 0x105). The increment gain
indicator, similarly, corresponds to the fine lower threshold bits,
except that it is asserted only if the input magnitude is less than
the value programmed in the fine lower threshold register after
the dwell time elapses. The dwell time is set by the 16-bit dwell
time value located at Address 0x10A and Address 0x10B and is
set in units of ADC input clock cycles ranging from 1 to 65,535.
The fine lower threshold register is a 13-bit register that is
compared with the magnitude at the output of the ADC.
IG
C_UT OR F_UT*
F_LT
DG
*C_UT AND F_UT DIFFER ONLY IN ACCURACY AND LATENCY.
NOTE: OUTPUTS FOLLOW THE INSTANTANEOUS SIGNAL LEVEL AND NOT THE ENVELOPE BUT ARE GUARANTEED ACTIVE FOR A MINIMUM OF 2 ADC CLOCK CYCLES.
Figure 65. Threshold Settings for C_UT, F_UT, IG, DG, and F_LT
RISE ABOVE F_LT
TIMER RESET BY
Rev. A | Page 32 of 72
DWELL TIME
This comparison is subject to the ADC clock latency but allows
a finer, more accurate comparison. The fine upper threshold
magnitude is defined by the following equation:
The decrement gain output works from the ADC fast detect
output pins, providing a fast indication of potential overrange
conditions. The increment gain uses the comparison at the
output of the ADC, requiring the input magnitude to remain
below an accurate, programmable level for a predefined period
before signaling external circuitry to increase the gain.
The operation of the increment gain output and the decrement
gain output is shown in Figure 65.
dBFS = 20 log(Threshold Magnitude/2
UPPER THRESHOLD (COARSE OR FINE)
DWELL TIME
FINE LOWER THRESHOLD
TIMER COMPLETES BEFORE
SIGNAL RISES ABOVE F_LT
13
)