AD9629BCPZ-80 Analog Devices Inc, AD9629BCPZ-80 Datasheet
AD9629BCPZ-80
Specifications of AD9629BCPZ-80
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AD9629BCPZ-80 Summary of contents
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FEATURES 1.8 V analog supply operation 1 3.3 V output supply SNR 71.3 dBFS at 9.7 MHz input 69.0 dBFS at 200 MHz input SFDR 95 dBc at 9.7 MHz input 83 dBc at 200 MHz input Low ...
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AD9629 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 Functional Block Diagram .............................................................. 1 Product Highlights ........................................................................... 1 Revision History ............................................................................... 2 General Description ......................................................................... 3 Specifications ..................................................................................... 4 DC Specifications ......................................................................... 4 AC Specifications .......................................................................... 5 Digital Specifications ...
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GENERAL DESCRIPTION The AD9629 is a monolithic, single channel 1.8 V supply, 12-bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS analog-to-digital conver- ter (ADC). It features a high performance sample-and-hold circuit and on-chip voltage reference. The product uses multistage differential pipeline architecture ...
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AD9629 SPECIFICATIONS DC SPECIFICATIONS AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty cycle clock, unless otherwise noted. Table 1. Parameter Temp RESOLUTION ...
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AC SPECIFICATIONS AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty cycle clock, unless otherwise noted. Table 2. 1 Parameter SIGNAL-TO-NOISE RATIO (SNR) ...
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AD9629 DIGITAL SPECIFICATIONS AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty cycle clock, unless otherwise noted. Table 3. Parameter DIFFERENTIAL CLOCK INPUTS ...
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SWITCHING SPECIFICATIONS AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty cycle clock, unless otherwise noted. Table 4. Parameter CLOCK INPUT PARAMETERS 1 ...
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AD9629 TIMING SPECIFICATIONS Table 5. Parameter Conditions SPI TIMING REQUIREMENTS t Setup time between the data and the rising edge of SCLK DS t Hold time between the data and the rising edge of SCLK DH t Period of the ...
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ABSOLUTE MAXIMUM RATINGS Table 6. Parameter AVDD to AGND DRVDD to AGND VIN+, VIN− to AGND CLK+, CLK− to AGND VREF to AGND SENSE to AGND VCM to AGND RBIAS to AGND CSB to AGND SCLK/DFS to AGND SDIO/PDWN to ...
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AD9629 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Table 8. Pin Function Description Pin No. Mnemonic Description 0 (EPAD) GND Exposed Paddle. The exposed paddle is the only ground connection. It must be soldered to the analog ground of the customer’s PCB ...
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TYPICAL PERFORMANCE CHARACTERISTICS AD9629-80 AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty cycle clock, unless otherwise noted. 0 80MSPS –15 9.7MHz @ ...
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AD9629 AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty cycle clock, unless otherwise noted. 100 SFDR 90 80 SNR ...
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AD9629-65 AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty cycle clock, unless otherwise noted. 0 65MSPS –15 9.7MHz @ –1dBFS SNR =70.3 ...
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AD9629 AD9629-40 AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty cycle clock, unless otherwise noted. 0 40MSPS –15 9.7MHz @ –1dBFS SNR ...
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AD9629-20 AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty cycle clock, unless otherwise noted. 0 20MSPS –15 9.7MHz @ –1dBFS SNR = ...
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AD9629 EQUIVALENT CIRCUITS AVDD VIN± Figure 26. Equivalent Analog Input Circuit AVDD VREF 7.5kΩ Figure 27. Equivalent VREF Circuit AVDD 375Ω SENSE Figure 28. Equivalent SENSE Circuit 5Ω CLK+ 15kΩ 15kΩ 5Ω CLK– Figure 29. Equivalent Clock Input Circuit 375Ω ...
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THEORY OF OPERATION The AD9629 architecture consists of a multistage, pipelined ADC. Each stage provides sufficient overlap to correct for flash errors in the preceding stage. The quantized outputs from each stage are combined into a final 12-bit result in ...
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AD9629 Differential Input Configurations Optimum performance is achieved while driving the AD9629 in a differential input configuration. For baseband applications, the AD8138, ADA4937-2, and ADA4938-2 differential drivers provide excellent performance and a flexible interface to the ADC. The output common-mode ...
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VOLTAGE REFERENCE A stable and accurate 1.0 V voltage reference is built into the AD9629. The VREF can be configured using either the internal 1.0 V reference or an externally applied 1.0 V reference voltage. The various reference modes are ...
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AD9629 CLOCK INPUT CONSIDERATIONS For optimum performance, clock the AD9629 sample clock inputs, CLK+ and CLK−, with a differential signal. The signal is typi- cally ac-coupled into the CLK+ and CLK− pins via a transformer or capacitors. These pins are ...
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Clock Duty Cycle Typical high speed ADCs use both clock edges to generate a variety of internal timing signals and result, may be sensitive to clock duty cycle. Commonly, a 50% duty cycle clock with ±5% tolerance is ...
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AD9629 In SPI mode, the AD9629 can be placed in power-down mode directly via the SPI port using the programmable external MODE pin. In non-SPI mode, power-down is achieved by asserting the PDWN pin high. In this state, ...
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BUILT-IN SELF-TEST (BIST) AND OUTPUT TEST The AD9629 includes a built-in self-test feature designed to enable verification of the integrity of each channel as well as to facilitate board level debugging. A built-in self-test (BIST) feature that verifies the integrity ...
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AD9629 SERIAL PORT INTERFACE (SPI) The AD9629 serial port interface (SPI) allows the user to configure the converter for specific functions or operations through a structured register space provided inside the ADC. The SPI gives the user added flexibility and ...
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HARDWARE INTERFACE The pins described in Table 13 constitute the physical interface between the programming device of the user and the serial port of the AD9629. The SCLK pin and the CSB pin function as inputs when using the SPI ...
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AD9629 MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Each row in the memory map register table (see Table 16) contains eight bit locations. The memory map is roughly divided into four sections: the chip configuration registers (Address 0x00 to ...
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MEMORY MAP REGISTER TABLE All address and bit locations that are not included in Table 16 are not currently supported for this device. Table 16. Addr Bit 7 (Hex) Register Name (MSB) Bit 6 Chip Configuration Registers 0x00 SPI port ...
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AD9629 Addr Bit 7 (Hex) Register Name (MSB) Bit 6 0x14 Output mode 00 = 3.3 V CMOS 10 = 1.8 V CMOS 0x15 Output adjust 3.3 V DCO drive strength stripe (default stripes ...
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MEMORY MAP REGISTER DESCRIPTIONS For additional information about functions controlled in Register 0x00 to Register 0xFF, see the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. USR2 (Register 0x101) Bit 3—Enable GCLK Detect Normally set high, this bit ...
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AD9629 APPLICATIONS INFORMATION DESIGN GUIDELINES Before starting design and layout of the AD9629 as a system recommended that the designer become familiar with these guidelines, which discuss the special circuit connections and layout requirements needed for certain pins. ...
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... OUTLINE DIMENSIONS PIN 1 INDICATOR 12° MAX 1.00 0.85 0.80 SEATING PLANE ORDERING GUIDE Model Temperature Range AD9629BCPZ- –40°C to +85° AD9629BCPZRL7-80 –40°C to +85° AD9629BCPZ-65 –40°C to +85° AD9629BCPZRL7-65 –40°C to +85° AD9629BCPZ-40 –40°C to +85°C ...
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AD9629 NOTES ©2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08540-0-10/09(0) Rev Page ...