AD9640-80EBZ Analog Devices Inc, AD9640-80EBZ Datasheet - Page 17

• Manufacturer Part Number: AD9640-80EBZ
• Description: 14Bit 80Msps Dual 1.8V PB Free ADC
• Manufacturer: Analog Devices Inc

Specifications of AD9640-80EBZ

• Design Resources: Interfacing ADL5534 to AD9640 High Speed ADC (CN0049)
• Number Of Adc's: 2
• Number Of Bits: 14
• Sampling Rate (per Second): 80M
• Data Interface: Serial
• Inputs Per Adc: 1 Differential
• Input Range: 2 Vpp
• Power (typ) @ Conditions: 550mW @ 80MSPS
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: AD9640
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9640-150EBZ - BOARD EVALUATION AD9640 150MSPS
• Lead Free Status / Rohs Status: Compliant

Table 12. Pin Function Descriptions (Interleaved Parallel LVDS Mode)
Pin No.
ADC Power Supplies
20, 64
1, 21
24, 57
36, 45, 46
0
ADC Analog
37
38
44
43
39
40
42
41
49
50
ADC Fast Detect Outputs
54
53
56
55
59
58
61
60
Mnemonic
DRGND
DRVDD
DVDD
AVDD
AGND,
Exposed Pad
VIN+A
VIN−A
VIN+B
VIN−B
VREF
SENSE
RBIAS
CML
CLK+
CLK−
FD0+
FD0−
FD1+
FD1−
FD2+
FD2−
FD3+
FD3−
Type
Ground
Supply
Supply
Supply
Ground
Input
Input
Input
Input
Input/Output
Input
Input/Output
Output
Input
Input
Output
Output
Output
Output
Output
Output
Output
Output
DRVDD
NOTES
1. NC = NO CONNECT.
2. THE EXPOSED THERMAL PAD ON THE BOTTOM OF THE PACKAGE PROVIDES
DCO–
DCO+
THE ANALOG GROUND FOR THE PART. THIS EXPOSED PAD MUST BE
CONNECTED TO GROUND FOR PROPER OPERATION.
D1–
D1+
D2–
D2+
D3–
D3+
D4–
D4+
D5–
D5+
D6–
D6+
D7–
10
12
13
14
15
16
11
1
2
3
4
5
6
7
8
9
Function
Digital Output Ground.
Digital Output Driver Supply (1.8 V to 3.3 V).
Digital Power Supply (1.8 V Nominal).
Analog Power Supply (1.8 V Nominal).
The exposed thermal pad on the bottom of the package provides the analog ground for the
part. This exposed pad must be connected to ground for proper operation.
Differential Analog Input Pin (+) for Channel A.
Differential Analog Input Pin (−) for Channel A.
Differential Analog Input Pin (+) for Channel B.
Differential Analog Input Pin (−) for Channel B.
Voltage Reference Input/Output.
Voltage Reference Mode Select. See Table 14 for details.
External Reference Bias Resistor.
Common-Mode Level Bias Output for Analog Inputs.
ADC Clock Input—True.
ADC Clock Input—Complement.
Channel A/Channel B LVDS Fast Detect Indicator 0—True. See Table 18 for details.
Channel A/Channel B LVDS Fast Detect Indicator 0—Complement. See Table 18 for details.
Channel A/Channel B LVDS Fast Detect Indicator 1—True. See Table 18 for details.
Channel A/Channel B LVDS Fast Detect Indicator 1—Complement. See Table 18 for details.
Channel A/Channel B LVDS Fast Detect Indicator 2—True. See Table 18 for details.
Channel A/Channel B LVDS Fast Detect Indicator 2—Complement. See Table 18 for details.
Channel A/Channel B LVDS Fast Detect Indicator 3—True. See Table 18 for details.
Channel A/Channel B LVDS Fast Detect Indicator 3—Complement. See Table 18 for details.
Figure 7. Pin Configuration, LFCSP LVDS (Top View)
PIN 1
INDICATOR
EXPOSED PADDLE, PIN 0
(BOTTOM OF PACKAGE)
PARALLEL LVDS
(Not to Scale)
Rev. B | Page 17 of 52
AD9640
TOP VIEW
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
SCLK/DFS
SDIO/DCS
AVDD
AVDD
VIN+B
VIN–B
RBIAS
CML
SENSE
VREF
VIN–A
VIN+A
AVDD
SMI SDFS
SMI SCLK/PDWN
SMI SDO/OEB
AD9640