AD9650-105EBZ Analog Devices Inc, AD9650-105EBZ Datasheet - Page 40

• Manufacturer Part Number: AD9650-105EBZ
• Description: 16Bit Hi SNR 105 Msps Dual ADC
• Manufacturer: Analog Devices Inc

Specifications of AD9650-105EBZ

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9650
MEMORY MAP REGISTER TABLE
All address and bit locations that are not included in Table 17 are not currently supported for this device.
Table 17. Memory Map Registers
Address
(Hex)
Chip Configuration Registers
0x00
0x01
0x02
Channel Index and Transfer Registers
0x05
0xFF
ADC Functions
0x08
0x09
0x0B
Register
Name
SPI port
configuration
(global)
Chip ID
(global)
Chip grade
(global)
Channel
index
Transfer
Power
modes (local)
Global clock
(global)
Clock divide
(global)
Bit 7
(MSB)
0
Open
Open
Open
1
Open
Open
Bit 6
LSB first
Open
Open
Open
Open
Open
Speed grade ID
001 = 105 MSPS
010 = 80 MSPS
011 = 65 MSPS
100 = 25 MSPS
Bit 5
Soft reset
Open
Open
External
power-
down pin
function
(local)
0 = pdwn
1 = stndby
Open
Open
(AD9650 = 0x32, default)
Bit 4
1
Open
Open
Open
Open
Open
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8-bit Chip ID[7:0]
Bit 3
1
Open
Open
Open
Open
Open
Open
Open
Bit 2
Soft reset
Open
Open
Open
Open
Clock divide ratio
000 = divide by 1
001 = divide by 2
010 = divide by 3
011 = divide by 4
100 = divide by 5
101 = divide by 6
110 = divide by 7
111 = divide by 8
Bit 1
LSB first
Open
Data
Channel
B
(default)
Open
Open
Internal power-
down mode (local)
00 = normal
operation
01 = full power-
down
10 = standby
11 = normal
operation
Bit 0
(LSB)
0
Open
Data
Channel
A
(default)
Transfer
Duty
cycle
stabilizer
(default)
Default
Value
(Hex)
0x18
0x32
0x03
0x00
0x80
0x01
0x00
The nibbles
Default
Notes/
Comments
are mirrored
so that LSB-
first mode or
MSB-first mode
registers
correctly,
regardless of
shift mode.
Read only.
Speed grade
ID used to
differentiate
devices; read
only.
Bits are set
to determine
which device
on the chip
receives the
next write
command;
applies to local
registers only.
Synchronously
transfers data
from the
master shift
register to the
slave.
Determines
various generic
modes of chip
operation.
Clock divide
values other
than 000
automatically
cause the duty
cycle stabilizer
to become
active.