AD9650-80EBZ Analog Devices Inc, AD9650-80EBZ Datasheet - Page 6

• Manufacturer Part Number: AD9650-80EBZ
• Description: 16Bit Hi SNR 80 Msps Dual ADC
• Manufacturer: Analog Devices Inc

Specifications of AD9650-80EBZ

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

UG-003
VREF
The default VREF configuration is to connect the SENSE pin to
AGND for internal VREF operation. This is done by connecting
Pin 4 and Pin 6 on Header J201. Table 2 summarizes the internal
VREF voltage for the different families of ADCs.
Table 2. Default VREF Configuration
Family Name
AD9650
AD9268
AD9269
The AD9650 and AD9269 families operate with a fixed reference.
For the AD9268 family, the reference voltage can be changed to
0.5 V for a 1.0 V p-p full-scale range by moving the SENSE pin
jumper connection on J201 from Pin 4 through Pin 6 to Pin 3
through Pin 4 (this connects the SENSE pin to the VREF pin).
To use the programmable reference mode for the AD9268 family, a
resistor divider can be set up by installing R204 and R205. The
jumper on J201 should be removed for this mode of operation.
See the data sheet of the specific part for the additional
information on using the programmable reference mode.
A separate unpopulated external reference option using the
AD1580
the evaluation board. To enable the external reference populate
CR201, U202, R202, R201, C201, and C202 with the values shown
in the Evaluation Board Schematics and Artwork section and
Bill of Materials section. The J201 jumper should be placed
between Pin 4 and Pin 2 to set the reference input to the
external reference mode.
RBIAS
RBIAS has a default setting of 10 kΩ (R206) to ground and is
used to set the ADC core bias current. Note that using a resistor
value other than a 10 kΩ, 1% resistor for RBIAS may degrade
the performance of the device.
Clock Circuitry for the AD9269 Family
The default clock input circuit on the AD9269 evaluation board
family uses a simple transformer-coupled circuit using a high
bandwidth 1:1 impedance ratio transformer (T601) that adds a low
amount of jitter to the clock path. The clock input is 50 Ω terminated
and ac-coupled to handle single-ended sine wave types of inputs.
The transformer converts the single-ended input to a differential
signal that is clipped by CR601 before entering the ADC clock inputs.
The AD9269 evaluation board family is by default set up to
be clocked through the transformer-coupled input network
from the crystal oscillator, Y601. This oscillator is a low phase
noise oscillator from Valpey Fisher (VFAC3-BHL-40MHz/
VFAC3-BHL-65MHz/VFAC3-BHL-80MHz). If a different
clock source is desired, remove J605 to disable the oscillator
from running and connect the external clock source to the
SMA connector, J602 (labeled ENCODE+).
reference and the
Internal VREF (V)
1.35
1
1
AD822
amplifier is also included on
Full-Scale Range (V p-p)
2.7
2
2
Rev. A | Page 6 of 40
Clock Circuitry for the AD9650 and the AD9268 Family
The default clock input circuit on the AD9650 and AD9268
family evaluation boards uses a similar circuit to the AD9269
family but uses a higher bandwidth 1:1 impedance ratio balun
(T602) that adds a low amount of jitter to the clock path. The
clock input is again 50 Ω terminated and ac-coupled to handle
single-ended sine wave types of inputs. The balun converts the
single-ended input to a differential signal that is clipped before
entering the ADC clock inputs.
The board is set by default to use an external clock generator. An
external clock source capable of driving a 50 Ω terminated input
should be connected to J602. This family is shipped from Valpey
Fisher with a low phase noise oscillator installed. The oscillator
frequency is set to match the rated speed of the part: 125 MHz,
105 MHz, or 80 MHz for the AD9268 family and 105 MHz,
80 MHz, 65 MHz, or 25 MHz for the AD9650 family. To enable
the oscillator, install J605, and to connect it into the clock path,
add a 0 Ω resistor at C610. R602 should also be removed to
remove the 50 Ω termination from the output of the oscillator.
A differential LVPECL clock driver output can also be used to
clock the ADC input using the
AD9517 into the clock path, populate R607 and R608 with 0 Ω
resistors and remove R609 and R610 to disconnect the default clock
path inputs. In addition, populate R731 and R732 with 0 Ω
resistors and remove R611 and R612 to disconnect the default
clock path outputs and insert the AD9517 LVPECL Output 3. The
AD9517 must be configured through the SPI controller software to
set up the PLL and other operation modes. Consult the AD9517
data sheet for more information about these and other options.
PDWN
To enable the power-down feature, add a shorting jumper across
J205 at Pin 1 and Pin 2 to connect the PDWN pin to DRVDD.
OE
To disable the outputs using the OE pin, add a shorting jumper
across J205 at Pin 3 and Pin 4 to connect the OE pin to DRVDD.
Non-SPI Mode
For users who want to operate the DUT without using SPI, remove
the shorting jumpers on J302. This disconnects the CS , SCLK/DFS,
and SDIO/DCS pins from the SPI control bus, allowing the DUT
to operate in non-SPI mode. In this mode, the SCLK/DFS and
SDIO/DCS pins take on their alternate functions to select the
data format and enable/disable the DCS. With the jumpers
removed, DCS is disabled; to enable DCS, add a shorting jumper
on J302 between Pin 2 to Pin 3. With the jumper removed, the
data format is set to offset binary. To set the data format to twos
complement, a jumper should be added on J302 between Pin 5
and Pin 6.
Evaluation Board User Guide
AD9517
(U701). To place the