AD9717-DPG2-EBZ Analog Devices Inc, AD9717-DPG2-EBZ Datasheet
AD9717-DPG2-EBZ
Specifications of AD9717-DPG2-EBZ
Related parts for AD9717-DPG2-EBZ
AD9717-DPG2-EBZ Summary of contents
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... Sleep mode: < 3.3 V Supply voltage: 1 3.3 V SFDR to Nyquist 84 dBc @ 1 MHz output 75 dBc @ 10 MHz output AD9717 NSD @ 1 MHz output, 125 MSPS, 2 mA: −151 dBc/Hz Differential current outputs on-chip auxiliary DACs CMOS inputs with single-port operation Output common mode: adjustable 1.2 V Small footprint 40-lead LFCSP RoHS-compliant package ...
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... AD9714/AD9715/AD9716/AD9717 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Product Highlights ........................................................................... 1 Revision History ............................................................................... 3 Functional Block Diagram .............................................................. 4 Specifications ..................................................................................... 5 DC Specifications ......................................................................... 5 Digital Specifications ................................................................... 7 AC Specifications .......................................................................... 8 Absolute Maximum Ratings ............................................................ 9 Thermal Resistance ...................................................................... 9 ESD Caution .................................................................................. 9 Pin Configurations and Function Descriptions ......................... 10 Typical Performance Characteristics ........................................... 18 Terminology .................................................................................... 31 Theory of Operation ...................................................................... 32 Serial Peripheral Interface (SPI) ................................................... 33 General Operation of the Serial Interface ...
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... Changes to Figure 84 and Theory of Operation Section ........... 32 Added Figure 85 to Figure 88; Renumbered Sequentially ......... 34 Changes to Pin Mode Section ........................................................ 35 Changes to Table 13 ........................................................................ 36 Changes to Table 14 ........................................................................ 37 AD9714/AD9715/AD9716/AD9717 Changes to Digital Interface Operation Section and Figure 89 to Figure 93 ........................................................................................... 40 Changes to Digital Data Latching and Retimer Block Section, Figure 94, and Retimer Section ..................................................... 41 Changes to Estimating the Overall DAC Pipeline Delay Section ...
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... I REF 100µA BAND AUX1DAC GAP 1 INTO 2 INTERLEAVED AUX2DAC I DATA DATA INTERFACE Q DATA CLOCK DIST Figure 1. Rev Page AD9717 IR SET 16kΩ IR CML 1kΩ TO RLIN 250Ω 500Ω IOUTN I DAC IOUTP 500Ω RLIP AVDD AVSS RLQP 500Ω ...
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... − − 0.25 0. 0.25 0. 1.08 0.98 1.025 1.08 0.98 10 Rev Page AD9716 AD9717 Typ Max Min Typ Max 12 14 ±0.4 ±1.7 ±0.2 ±1.0 ±0.4 ±1.8 ±0.3 ±1.3 ±0.4 ±1.2 ±0.2 ±1.0 ±0.4 ±1.5 ±0.25 ±1 − − 2 2.5 0 +1.2 −0 ...
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... Rev Page AD9716 AD9717 Min Typ Max Min Typ 0.1 1.25 0.1 0.1 1.0 0 −1 +1 −1 1.7 3.5 1.7 1.7 3.5 1.7 1.7 1.9 1.7 1.7 3.5 1 ...
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... V Q Channel or DCLKIO Falling Edge Setup Hold 1 Channel or DCLKIO Rising Edge Setup Hold 3 Channel or DCLKIO Falling Edge Setup Hold 3 Channel or DCLKIO Rising Edge Setup Hold AD9714/AD9715/AD9716/AD9717 = 2 mA, maximum sample rate, unless xOUTFS Min 2.1 2.1 Rev Page Typ Max Unit 0.9 V 125 ...
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... AD9716 AD9717 Min Typ Max Min Typ Max −149 −152 −137 −141 −71 −71 −72 − mA, maximum sample rate, unless AD9716 AD9717 Min Typ Max Min Typ Max −146 −148 −131 −132 −68 −68 −68 −68 Unit dBc dBc dBc ...
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... Storage Temperature Range 1 n stands for 7 for the AD9714, 9 for the AD9715, 11 for the AD9716, and 13 for the AD9717. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied ...
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... AD9714/AD9715/AD9716/AD9717 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS Table 7. AD9714 Pin Function Descriptions Pin No. Mnemonic Description DB[5:2] Digital Inputs. 5 DVDDIO Digital I/O Supply Voltage (1 3.3 V Nominal). 6 DVSS Digital Common. 7 DVDD Digital Core Supply Voltage (1.8 V). Strap DVDD to DVDDIO at 1 DVDDIO > 1.8 V, bypass DVDD with a 1.0 μ ...
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... The exposed pad is connected to AVSS and should be soldered to the ground plane. Exposed metal at the (EPAD) package corners is connected to this pad. resistor recommended to leave this pin unconnected. When the internal on chip (IR CML Rev Page AD9714/AD9715/AD9716/AD9717 ) is enabled, this pin is connected to the CML ) is disabled, this pin is the full- SET ) is enabled, this pin is the auxiliary Q DAC ...
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... AD9714/AD9715/AD9716/AD9717 Table 8. AD9715 Pin Function Descriptions Pin No. Mnemonic Description DB[7:4] Digital Inputs. 5 DVDDIO Digital I/O Supply Voltage (1 3.3 V Nominal). 6 DVSS Digital Common. 7 DVDD Digital Core Supply Voltage (1.8 V). Strap DVDD to DVDDIO at 1 DVDDIO > 1.8 V, bypass DVDD with a 1.0 μF capacitor; however, do not otherwise connect it. The LDO should not drive external loads. ...
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... The exposed pad is connected to AVSS and should be soldered to the ground plane. Exposed metal at the (EPAD) package corners is connected to this pad. resistor recommended to leave this pin unconnected. When the internal on chip (IR CML Rev Page AD9714/AD9715/AD9716/AD9717 ) is enabled, this pin is connected to the CML ) is disabled, this pin is the full- SET ) is enabled, this pin is the auxiliary Q DAC ...
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... AD9714/AD9715/AD9716/AD9717 Table 9. AD9716 Pin Function Descriptions Pin No. Mnemonic Description DB[9:6] Digital Inputs. 5 DVDDIO Digital I/O Supply Voltage (1 3.3 V Nominal). 6 DVSS Digital Common. 7 DVDD Digital Core Supply Voltage (1.8 V). Strap DVDD to DVDDIO at 1 DVDDIO > 1.8 V, bypass DVDD with a 1.0 μF capacitor; however, do not otherwise connect it. The LDO should not drive external loads. ...
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... The exposed pad is connected to AVSS and should be soldered to the ground plane. Exposed metal at the (EPAD) package corners is connected to this pad. resistor recommended to leave this pin unconnected. When the internal on chip (IR CML Rev Page AD9714/AD9715/AD9716/AD9717 ) is enabled, this pin is connected to the CML ) is disabled, this pin is the full- SET ) is enabled, this pin is the auxiliary Q DAC ...
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... AD9714/AD9715/AD9716/AD9717 Table 10. AD9717 Pin Function Descriptions Pin No. Mnemonic Description DB[11:8] Digital Inputs. 5 DVDDIO Digital I/O Supply Voltage (1 3.3 V Nominal). 6 DVSS Digital Common. 7 DVDD Digital Core Supply Voltage (1.8 V). Strap DVDD to DVDDIO at 1 DVDDIO > 1.8 V, bypass DVDD with a 1.0 μF capacitor; however, do not otherwise connect it. The LDO should not drive external loads. ...
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... The exposed pad is connected to AVSS and should be soldered to the ground plane. Exposed metal at the (EPAD) package corners is connected to this pad. resistor recommended to leave this pin unconnected. When the internal on chip (IR CML Rev Page AD9714/AD9715/AD9716/AD9717 ) is enabled, this pin is connected to the CML ) is disabled, this pin is the full- SET ) is enabled, this pin is the auxiliary Q DAC ...
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... Figure 9. AD9717 Postcalibration INL at 1.8 V (DVDD = 1.8 V) 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 0 2048 4096 6144 Figure 10. AD9717 Postcalibration DNL at 1.8 V (DVDD = 1.8 V) 1.75 1.25 0.75 0.25 –0.25 –0.75 –1.25 –1.75 0 2048 4096 Figure 11. AD9717 Postcalibration INL at 3.3 V (DVDD = 1.8 V) Rev ...
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... CODE Figure 12. AD9717 Precalibration DNL at 3.3 V 0.4 0.3 0.2 0.1 0 –0.1 –0.2 –0.3 –0.4 0 512 1024 1536 2048 2560 3072 CODE Figure 13. AD9716 Precalibration INL at 1.8 V ...
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... AD9714/AD9715/AD9716/AD9717 0.4 0.3 0.2 0.1 0 –0.1 –0.2 –0.3 –0.4 0 512 1024 1536 2048 2560 CODE Figure 18. AD9716 Precalibration INL at 3.3 V 0.4 0.3 0.2 0.1 0 –0.1 –0.2 –0.3 –0.4 0 512 1024 1536 2048 2560 CODE Figure 19. AD9716 Precalibration DNL at 3.3 V 0.13 0.08 0.03 – ...
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... Figure 25. AD9715 Precalibration INL at 3.3 V 0.13 0.08 0.03 –0.02 –0.07 –0.12 0 128 256 384 512 640 768 CODE Figure 26. AD9715 Precalibration DNL at 3.3 V AD9714/AD9715/AD9716/AD9717 0.13 0.08 0.03 –0.02 –0.07 –0.12 896 1024 0 128 Figure 27. AD9715 Postcalibration DNL at 1.8 V 0.13 0.08 0.03 –0.02 – ...
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... AD9714/AD9715/AD9716/AD9717 0.025 0.020 0.015 0.010 0.005 0 –0.005 –0.010 –0.015 –0.020 –0.025 112 128 144 160 CODE Figure 30. AD9714 Precalibration INL at 1.8 V 0.025 0.020 0.015 0.010 0.005 0 –0.005 –0.010 –0.015 –0.020 –0.025 112 128 144 160 CODE Figure 31. AD9714 Precalibration DNL at 1.8 V ...
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... Figure 38. AD9717 Noise Spectral Density at Three Temperatures, 1.8 V 176 192 208 224 240 256 Figure 40. AD9714/AD9715/AD9716/AD9717 Noise Spectral Density at 3.3 V +25° Figure 41. AD9717 Noise Spectral Density at Three Temperatures, 3.3 V Rev Page AD9714/AD9715/AD9716/AD9717 0.025 0.020 0.015 0.010 0.005 0 –0.005 –0.010 –0.015 –0.020 –0.025 ...
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... OUT Figure 42. AD9717 Noise Spectral Density at Two Output Currents, 1.8 V –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 START 1MHz 1.5MHz/DIV Figure 43. AD9717 Two Tone Spectrum, 1 ...
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... OUT Figure 48. AD9717 IMD at Three Temperatures, 1 –3dB –6dB 70 64 0dB (MHz) IN Figure 49. AD9717 IMD at Three Digital Input Levels, 1 1mA 72 2mA (MHz) OUT Figure 50. AD9717 IMD at Two Output Currents, 1.8 V AD9714/AD9715/AD9716/AD9717 Figure 51. AD9717 IMD at Three Temperatures, 3 ...
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... START 1MHz 1.4MHz/DIV Figure 57. AD9717 Single-Tone Spectrum, 3 AD9717 90 AD9716 AD9715 87 AD9714 (MHz) OUT Figure 58. AD9714/AD9715/AD9716/AD9717 SFDR at 3 3.3V, +85° 3.3V, –40°C 3.3V, +25° (MHz) OUT Figure 59. AD9717 SFDR at Three Temperatures, 3.3 V STOP 15MHz ...
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... REF CARRIER POWER –19.81dBm/4.03420MHz RCC FILTER: OFF FILTER ALPHA 0.22 OFFSET INTEG LOWER dBc dBm FREQ BW 1. –19.81dBm 5.000MHz 3.840MHz –70.32 –90.13 –72.61 –92.42 2. –85.75dBm 10.00MHz 3.840MHz –71.81 –91.61 –71.60 –91.41 15.00MHz 3.840MHz –72.59 –92.40 –65.50 –85.31 Figure 62. AD9717 One-Carrier ACLR, 1.8 V AD9714/AD9715/AD9716/AD9717 ...
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... PRECAL 1mA POSTCAL –70 2mA POSTCAL 4mA PRECAL –75 4mA POSTCAL – (MHz) OUT Figure 70. AD9717 One-Carrier W-CDMA Second ACLR, 3.3 V –60 1mA PRECAL –65 1mA POSTCAL 2mA PRECAL –70 4mA PRECAL 2mA POSTCAL –75 4mA POSTCAL – (MHz) OUT Figure 71 ...
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... Figure 76. AD9717 Two-Carrier W-CDMA First ACLR, 3.3 V –55 –60 –65 –70 – Figure 77. AD9717 Two-Carrier W-CDMA Second ACLR, 3.3 V Rev Page AC-COUPLED:UNSPECIFIED BELOW 20MHz SPAN 38.84MHz VBW 300kHz SWEEP 126ms (601pts) FILTER ALPHA 0.22 OFFSET INTEG LOWER UPPER FREQ BW ...
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... PRECAL 1mA POSTCAL 2mA PRECAL 2mA POSTCAL 4mA POSTCAL 4mA PRECAL (MHz) OUT Figure 81. AD9717 Two-Carrier W-CDMA Third ACLR, 3 128 256 384 512 640 768 CODE Figure 82. AUXDAC INL TOTAL CURRENT @ 1mA OUT TOTAL CURRENT @ 2mA OUT TOTAL CURRENT @ 4mA OUT ...
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... Celsius (ppm FSR/°C). For reference drift, the drift is reported in parts per million per degree Celsius (ppm/°C). AD9714/AD9715/AD9716/AD9717 Power Supply Rejection Power supply rejection is the maximum change in the full-scale output as the supplies are varied from minimum to maximum specified voltages ...
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... The analog and digital I/O sections of the AD9714/AD9715/ AD9716/AD9717 have separate power supply inputs (AVDD and DVDDIO) that can operate independently over a 1 3.3 V range. The core digital section requires 1 optional on-chip ...
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... AD9714/AD9715/AD9716/AD9717. Single or multiple byte transfers are supported, as well as MSB first or LSB first transfer formats. The serial interface port of the AD9714/ AD9715/AD9716/AD9717 is configured as a single I/O pin on the SDIO pin. GENERAL OPERATION OF THE SERIAL INTERFACE There are two phases to a communications cycle on the AD9714/ AD9715/AD9716/AD9717 ...
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... LSB first mode is active. SERIAL PORT OPERATION The serial port configuration of the AD9714/AD9715/AD9716/ AD9717 is controlled by Register 0x00 important to note that the configuration changes immediately upon writing to the last bit of the register. For multibyte transfers, writing to this register can occur during the middle of the communications cycle ...
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... QAUXEN QAUXRNG[1:0] IAUXEN IAUXRNG[1:0] Reserved PRELDQ PRELDI CALSELQ CALSELI CALSTATQ CALSTATI Reserved Reserved CALRSTQ CALRSTI CALEN CLKMODEQ[1:0] Searching Rev Page AD9714/AD9715/AD9716/AD9717 Bit 3 Bit 2 Bit 1 I DACOFF QCLKOFF ICLKOFF SIMULBIT DCI_EN DCOSGL I DACGAIN[5:0] IRSET[5:0] IRCML[5:0] Q DACGAIN[5:0] QRSET[5:0] QRCML[5:0] QAUXDAC[7:0] QAUXOFS[2:0] QAUXDAC[9:8] IAUXDAC[7:0] ...
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... AD9714/AD9715/AD9716/AD9717 SPI REGISTER DESCRIPTIONS Reading these registers returns previously written values for all defined register bits, unless otherwise noted. Table 14. Register Address Bit Name SPI Control 0x00 6 LSBFIRST 5 Reset 4 LNGINS Power-Down 0x01 7 LDOOFF 6 LDOSTAT 5 PWRDN 4 Q DACOFF 3 I DACOFF 2 QCLKOFF 1 ICLKOFF ...
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... QAUXEN 6:5 QAUXRNG[1:0] 4:2 QAUXOFS[2:0] 1:0 QAUXDAC[9:8] AD9714/AD9715/AD9716/AD9717 Description 0 (default): IR resistor value for I channel is set by an external resistor connected SET to the FADJI/AUXI pin. Nominal value for this external resistor is 16 kΩ. 1: enables the on-chip IR value to be changed for I channel. SET Changes the value of the on-chip IR resistor for I channel ...
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... AD9714/AD9715/AD9716/AD9717 Register Address Bit Name AUXDAC I 0x0B 7:0 IAUXDAC[7:0] AUX CTLI 0x0C 7 IAUXEN 6:5 IAUXRNG[1:0] 4:2 IAUXOFS[2:0] 1:0 IAUXDAC[9:8] Reference 0x0D 5:0 RREF[5:0] Resistor Cal Control 0x0E 7 PRELDQ 6 PRELDI 5 CALSELQ 4 CALSELI 3 CALCLK 2:0 DIVSEL[2:0] Cal Memory 0x0F 7 CALSTATQ 6 CALSTATI 3:2 CALMEMQ[1:0] ...
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... Searching 3 Reacquire 2 CLKMODEN 1:0 CLKMODEI[1:0] Version 0x1F 7:0 Version[7:0] AD9714/AD9715/AD9716/AD9717 Description 0 (default): no action. 1: clear CALSTATQ. 0 (default): no action. 1: clear CALSTATI. 0 (default): no action. 1: initiate device self-calibration. 0 (default): no action. 1: write to static memory (calibration coefficients). 0 (default): no action. 1: read from static memory (calibration coefficients). 0 (default): no action. ...
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... Digital data for the I and Q DACs is supplied over a single parallel bus (DB[n:0), where for the AD9714, 9 for the AD9715, 11 for the AD9716, and 13 for the AD9717) accompanied by a qualifying clock (DCLKIO). The I and Q data are provided to the chip in an interleaved double data rate (DDR) format ...
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... DB[n:0] (INPUT) DCLKIO-INT NOTES: 1. DB[n:0], WHERE FOR THE AD9714, 9 FOR THE AD9715, 11 FOR THE AD9716, AND 13 FOR THE AD9717. Figure 94. Simplified Diagram of AD9714/AD9715/AD9716/AD9717 Timing DIGITAL DATA LATCHING AND RETIMER BLOCK The AD9714/AD9715/AD9716/AD9717 have two clock inputs, DCLKIO and CLKIN. The CLKIN is the analog clock whose ...
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... D- 2.5 clock cycles (½ clock cycle to D- clock cycle to D-FF 3, and 1 clock cycle to D-FF 4). This latency for the AD9714/ AD9715/AD9716/AD9717 is case specific and needs to be calcu- lated based on the RETIMER-CLK phase that is automatically selected or manually forced. ...
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... I The control amplifier allows a 2.5:1 adjustment span of I from setting I (set xOUTFS the power dissipation of the AD9714/AD9715/AD9716/AD9717, which is proportional to I section). The second benefit relates to the ability to adjust the I DAC OR output over range with 0.25 dB steps, which is useful for Q DAC controlling the transmitted power ...
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... DAC CODE = 2 xOUTFS where 10, 12 for the AD9714, AD9715, AD9716, and AD9717, respectively), while IOUTN and QOUTN, the complementary outputs, provide no current. The current outputs appearing at the positive DAC outputs, IOUTP and QOUTP, and at the negative DAC outputs, IOUTN and QOUTN, ...
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... SELF-CALIBRATION The AD9714/AD9715/AD9716/AD9717 have a self-calibration feature that improves the DNL of the device. Performing a self- calibration on the device improves device performance in low frequency applications. The device performance in applications where the analog output frequencies are above 5 MHz are generally influenced more by dynamic device behavior than by DNL and, in these cases, self-calibration is unlikely to provide much benefit ...
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... AD9714/AD9715/AD9716/AD9717 COARSE GAIN ADJUSTMENT Option 1 A coarse full-scale output current adjustment can be achieved using the lower six bits in Register 0x0D. This adds or subtracts up to 20% from the band gap voltage on Pin 34 (REFIO), and the voltage on the FSADJx resistors tracks this change result, the DAC full-scale current varies by the same amount. ...
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... USING THE INTERNAL TERMINATION RESISTORS The AD9717/AD9716/AD9715/AD9714 have four 500 Ω termination internal resistors (two for each DAC output). To use these resistors to convert the DAC output current to a voltage, connect each DAC output pin to the adjacent load pin. For example, on the I DAC, IOUTP must be shorted to RLIP and IOUTN must be shorted to RLIN ...
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... Note that approximately half the signal power is dissipated across R SINGLE-ENDED BUFFERED OUTPUT USING AN OP AMP An op amp such as the a single-ended current-to-voltage conversion, as shown in Figure 104. The AD9714/AD9715/AD9716/AD9717 are config- ured with a pair of series resistors, R distortion performance, R resistor, R formula V OUT ...
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... R B Figure 105. Single-Supply Differential Buffer AUXILIARY DACs The DACs of the AD9714/AD9715/AD9716/AD9717 feature two versatile and independent 10-bit auxiliary DACs suitable for dc offset correction and similar tasks. Because the AUXDACs are driven through the SPI port, they should never be used in timing-critical applications, such as inside analog feedback loops ...
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... The quadrature modulator has a finite dc referred offset, as well as coupling from its LO port to the signal inputs. These can lead to a significant spectral spur at the frequency of the quadrature modulator LO. The AD9714/AD9715/AD9716/AD9717 have the capability to correct for both of these analog degradations. However, MODULATOR V+ understand that these degradations drift over temperature; ...
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... FREQUENCY (MHz) Figure 111. AD9714/AD9715/AD9716/AD9717 and ADL5370 with a Single- Tone Signal at 450 MHz, Gain and LO Compensation Optimized Rev Page 450.0 451.0 452.5 450.0 451.0 452.5 ...
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... MODULATOR The evaluation board contains an Analog Devices, Inc., ADL5370 quadrature modulator. The AD9714/AD9715/ AD9716/AD9717 and the ADL5370 provide an easy-to- interface DAC/modulator combination that can be easily characterized on the evaluation board. Solderable jumpers can be configured to evaluate the single-ended or differential outputs of the AD9714/AD9715/AD9716/AD9717. This setup ...
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... EVALUATION BOARD SHEMATICS AND ARTWORK SCHEMATICS RC0603 CC0603 RC0603 RC0603 CC0603 CC0603 Figure 112. Power Supplies and Filters Rev Page AD9714/AD9715/AD9716/AD9717 07265-184 RC0603 CC0603 RC0603 CC0603 ...
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... AD9714/AD9715/AD9716/AD9717 DNP RNETCTS743-8 RP1 FEMALE ANGLE RIGHT HEADER Figure 113. Digital Inputs Rev Page 07265-185 RNETCTS743 DNP RP5 ...
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... RC0402 RC0402 RC0402 RC0402 RC0402 CC0402 CC0402 RC0402 RC0402 Figure 114. Clock Input and DUT AD9714/AD9715/AD9716/AD9717 RC0603 R7 Rev Page 07265-186 ...
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... AD9714/AD9715/AD9716/AD9717 RC0603 RC0603 RC0603 RC0603 RC0603 CC0402 RC0603 RC0603 RC0603 RC0603 Figure 115. IOUT Network and FSADJ1 Rev Page 07265-187 CC0805 CC0603 CC0603 RC0603 JP12 RC0603 RC0603 RC0805 JP9 ERA6Y ERA6YEB323V, RC0805 JP8 ERA6Y ERA6YEB323V, RC0805 JP7 ERA6Y ERA6YEB323V, ...
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... RC0603 RC0603 RC0603 RC0603 RC0603 RC0603 RC0603 RC0603 AD9714/AD9715/AD9716/AD9717 RC0603 RC0603 Figure 116. QOUT Network and FSADJ2 Rev Page 07265-188 RC0603 JP77 RC0603 RC0603 RC0805 JP20 ERA6Y ERA6YEB323V, RC0805 JP16 ERA6Y ERA6YEB323V, RC0805 JP21 ERA6Y ERA6YEB323V, ...
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... AD9714/AD9715/AD9716/AD9717 S3 S1 GRN MLX-0532610571 Figure 117. SPI Port Rev Page 07265-189 ...
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... C54 100PF C53 100PF 1k RC0603 R24 Figure 118. Modulated Output Rev Page AD9714/AD9715/AD9716/AD9717 C73 100PF ETC1-1-13 1k RC0603 R61 07265-190 ...
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... AD9714/AD9715/AD9716/AD9717 CC0402 RC0805 CC0402 HSMS-281C Figure 119. Clock Driver Chip Rev Page 07265-191 ...
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... SILKSCREENS AD9714/AD9715/AD9716/AD9717 Figure 120. Layer 2, Ground Plane Rev Page ...
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... AD9714/AD9715/AD9716/AD9717 Figure 121. Layer 3, Power Plane Rev Page ...
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... AD9714/AD9715/AD9716/AD9717 Figure 122. Assembly—Primary Side Rev Page ...
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... AD9714/AD9715/AD9716/AD9717 Figure 123. Assembly—Secondary Side Rev Page ...
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... AD9714/AD9715/AD9716/AD9717 Figure 124. Solder Mask—Primary Side with Socket Rev Page ...
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... AD9714/AD9715/AD9716/AD9717 Figure 125. Solder Mask—Secondary Side Rev Page ...
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... AD9714/AD9715/AD9716/AD9717 Figure 126. Hard Gold Plated with Bumps and Socket Rev Page ...
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... AD9714/AD9715/AD9716/AD9717 Figure 127. Primary Side Paste Rev Page ...
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... AD9714/AD9715/AD9716/AD9717 Figure 128. Secondary Side Paste Rev Page ...
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... AD9714/AD9715/AD9716/AD9717 Figure 129. Silkscreen—Primary Side Rev Page ...
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... AD9714/AD9715/AD9716/AD9717 Figure 130. Silkscreen—Secondary Side Rev Page ...
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... AD9714/AD9715/AD9716/AD9717 Figure 131. Layer 1—Primary Side Rev Page ...
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... AD9714/AD9715/AD9716/AD9717 Figure 132. Layer 4—Secondary Side Rev Page ...
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... AD9714/AD9715/AD9716/AD9717 Figure 133. Immersion Gold, No Socket, No Bumps Rev Page ...
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... AD9714/AD9715/AD9716/AD9717 Figure 134. Solder Mask—Primary Side, No Socket Rev Page ...
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... AD9714/AD9715/AD9716/AD9717 BILL OF MATERIALS Table 18. Qty Reference Designator Device 6 C1, C2, C4, C5, C32, C57 CAPSMDA 17 C3, C6, C7, C8, C9, C10, C11, CC0603 C15, C16, C22, C24, C26, C27, C48, C60, C61, C107 11 C12, C14, C17, C18, C20, CC0603 C21, C31, C37, C39, C86, C88 ...
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... R88, R89 RC0402 2 R90, R109 RC0402 1 R91 RC0805 2 R111, R112 RC0603 1 R114 RC0402 2 RP1, RP5 RNETCTS743-8 AD9714/AD9715/AD9716/AD9717 Package Description LC1812 EXC-CL4532U1 LC1008 1.8 μH, 10% LC1008 DNP LC1210 EXC-CL3225U1 USB-MINIB USB mini 5-pin Molex 0532610571 1.25 mm, 5-pin wire- to-board connector RC0805 32 kΩ, 0.1% resistor RC0603 76.8 kΩ ...
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... TP5, TP8, TP12, TP13, LOOPMINI TP16, TP24, TP39, TP42 1 TP2 LOOPMINI 12 TP4, TP6, TP7, TP9, TP10, LOOPMINI TP11, TP14, TP15, TP21, TP23, TP41, TP43 1 TP40 LOOPMINI 1 U1 40-lead LFCSP, AD9717 5 U2, U4, U6, U7, U11 ADP3334 1 U3 USB-PIC18F4550-I/ML-ND 2 U5, U14 ADG3304BRUZ 1 U8 74LVC1G34 1 U9 ADL5370 ...
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... Package Description 40-Lead LFCSP_VQ 40-Lead LFCSP_VQ 40-Lead LFCSP_VQ 40-Lead LFCSP_VQ 40-Lead LFCSP_VQ 40-Lead LFCSP_VQ 40-Lead LFCSP_VQ 40-Lead LFCSP_VQ Evaluation Board Evaluation Board Evaluation Board Evaluation Board Rev Page AD9714/AD9715/AD9716/AD9717 0.60 MAX PIN 1 INDICATOR 4.25 EXPOSED 4.10 SQ PAD 3.95 (BOT TOM VIEW) ...
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... AD9714/AD9715/AD9716/AD9717 NOTES ©2008–2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07265-0-3/09(A) Rev Page ...