AD9850/FSPCB Analog Devices Inc, AD9850/FSPCB Datasheet - Page 3

• Manufacturer Part Number: AD9850/FSPCB
• Description: D/A Converter (D-A) IC
• Manufacturer: Analog Devices Inc

Specifications of AD9850/FSPCB

• No. Of Bits: 32 Bit
• Mounting Type: Surface Mount
• Interface Type: Serial, Parallel
• Package / Case: 28-SSOP
• Rohs Status: RoHS non-compliant
• Main Purpose: Timing, Direct Digital Synthesis (DDS)
• Utilized Ic / Part: AD9850/FS
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -
• Lead Free Status / Rohs Status: Not Compliant

Parameter
CMOS LOGIC INPUTS (Including CLKIN)
POWER SUPPLY (A
*Tested by measuring output duty cycle variation.
Specifications subject to change without notice.
REV. H
TIMING CHARACTERISTICS*
Parameter
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
*Control functions are asynchronous with CLKIN.
Specifications subject to change without notice.
DS
DH
WH
WL
WD
CD
FH
FL
CF
FD
RH
RL
RS
OL
RR
Logic 1 Voltage, 5 V Supply
Logic 1 Voltage, 3.3 V Supply
Logic 0 Voltage
Logic 1 Current
Logic 0 Current
Input Capacitance
+V
P
P
DISS
DISS
62.5 MHz Clock, 3.3 V Supply
110 MHz Clock, 3.3 V Supply
62.5 MHz Clock, 5 V Supply
125 MHz Clock, 5 V Supply
62.5 MHz Clock, 3.3 V Supply
110 MHz Clock, 3.3 V Supply
62.5 MHz Clock, 5 V Supply
125 MHz Clock, 5 V Supply
5 V Supply
3.3 V Supply
(Data Setup Time)
(Data Hold Time)
(W_CLK Minimum Pulse Width High)
(W_CLK Minimum Pulse Width Low)
(W_CLK Delay after FQ_UD)
(CLKIN Delay after FQ_UD)
(FQ_UD High)
(FQ_UD Low)
(Output Latency from FQ_UD)
Frequency Change
Phase Change
(FQ_UD Minimum Delay after W_CLK)
(CLKIN Delay after RESET Rising Edge)
(RESET Falling Edge after CLKIN)
(Minimum RESET Width)
(RESET Output Latency)
(Recovery from RESET)
Wake-Up Time from Power-Down Mode
S
Current @
@
Power-Down Mode
OUT
= 1/3 CLKIN)
(V
S
= 5 V
5% except as noted, R
Temp
25°C
25°C
25°C
25°C
25°C
25°C
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Temp
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
25°C
–3–
Test Level
I
IV
IV
I
I
V
VI
VI
VI
VI
VI
VI
VI
VI
V
V
Test Level
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
V
SET
= 3.9 k )
Min
3.5
3.5
3.5
3.5
7.0
3.5
7.0
7.0
18
13
7.0
3.5
3.5
5
13
2
Min
3.5
2.4
AD9850BRS
AD9850BRS
Typ
5
Typ
3
30
47
44
76
100
155
220
380
30
10
Max
Max
0.8
12
12
48
60
64
96
160
200
320
480
Unit
ns
ns
ns
ns
ns
ns
ns
ns
CLKIN Cycles
CLKIN Cycles
ns
ns
ns
CLKIN Cycles
CLKIN Cycles
CLKIN Cycles
µs
Unit
V
V
V
µA
µA
pF
mA
mA
mA
mA
mW
mW
mW
mW
mW
mW
AD9850