AD9985ABSTZ-110 Analog Devices Inc, AD9985ABSTZ-110 Datasheet - Page 19

• Manufacturer Part Number: AD9985ABSTZ-110
• Description: IC,Data Acquisition Signal Conditioner,3-CHANNEL,8-BIT,CMOS,QFP,80PIN,PLASTIC
• Manufacturer: Analog Devices Inc

Specifications of AD9985ABSTZ-110

• Applications: Video
• Interface: Serial Port
• Voltage - Supply: 2.2 V ~ 3.45 V
• Package / Case: 80-LQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

2-WIRE SERIAL CONTROL REGISTER DETAIL CHIP
IDENTIFICATION
00
PLL DIVIDER CONTROL
01
02
7–0
An 8-bit register that represents the silicon revision.
7–0
The 8 most significant bits of the 12-bit PLL divide
ratio PLLDIV. The operational divide ratio is
PLLDIV + 1.
The PLL derives a master clock from an incoming
Hsync signal. The master clock frequency is then
divided by an integer value, such that the output is
phase-locked to Hsync. This PLLDIV value
determines the number of pixel times (pixels plus
horizontal blanking overhead) per line. This is
typically 20% to 30% more than the number of active
pixels in the display.
The 12-bit value of the PLL divider supports divide
ratios from 2 to 4095. The higher the value loaded in
this register, the higher the resulting clock frequency
with respect to a fixed Hsync frequency.
VESA has established some standard timing
specifications that assist in determining the value for
PLLDIV as a function of horizontal and vertical
display resolution and frame rate (Table 9).
However, many computer systems do not conform
precisely to the recommendations, and these numbers
should be used only as a guide. The display system
manufacturer should provide automatic or manual
means for optimizing PLLDIV. An incorrectly set
PLLDIV will usually produce one or more vertical
noise bars on the display. The greater the error, the
greater the number of bars produced.
The power-up default value of PLLDIV is 1693
(PLLDIVM = 69H, PLLDIVL = DxH).
The AD9985 updates the full divide ratio only when
the LSBs are changed. Writing to the MSB by itself will
not trigger an update.
7–4
The 4 least significant bits of the 12-bit PLL divide
ratio PLLDIV. The operational divide ratio is
PLLDIV + 1.
The power-up default value of PLLDIV is 1693
(PLLDIVM = 69H, PLLDIVL = DxH). The AD9985
updates the full divide ratio only when this register is
written to.
Chip Revision
PLL Divide Ratio LSBs
PLL Divide Ratio MSBs
Rev. 0 | Page 19 of 32
CLOCK GENERATOR CONTROL
03
Table 11 shows the pixel rates for each VCO range setting. The
Table 11. VCO Ranges
PV1
0
0
1
1
03
Table 12. Charge Pump Currents
CURRENT
000
001
010
011
100
101
110
111
The power-up default value is current = 001.
04
7–6
Two bits that establish the operating range of the clock
generator.
VCORNGE must be set to correspond with the
desired operating frequency (incoming pixel rate).
The PLL gives the best jitter performance at high
frequencies. For this reason, to output low pixel rates
and still get good jitter performance, the PLL actually
operates at a higher frequency but then divides down
the clock rate afterwards.
PLL output divisor is automatically selected with the
VCO range setting.
The power-up default value is 01.
5–3
Three bits that establish the current driving the loop
filter in the clock generator.
CURRENT must be set to correspond with the desired
operating frequency (incoming pixel rate).
7–3
A 5-bit value that adjusts the sampling phase in 32
steps across one pixel time. Each step represents an
11.25° shift in sampling phase.
The power-up default value is 16.
PV0
0
1
0
1
VCO Range Select
CURRENT Charge Pump Current
Clock Phase Adjust
AD9985KSTZ
12–32
32–64
64–110
110–140
Pixel Clock Range (MHz)
Current (µA)
50
100
150
250
350
500
750
1500
AD9985BSTZ
12–30
30–60
60–110
AD9985