ADA4062-4ACPZ-RL Analog Devices Inc, ADA4062-4ACPZ-RL Datasheet - Page 16

• Manufacturer Part Number: ADA4062-4ACPZ-RL
• Description: Quad36vLowPwrLowCostJFETInputAmp
• Manufacturer: Analog Devices Inc

Specifications of ADA4062-4ACPZ-RL

• Amplifier Type: J-FET
• Number Of Circuits: 4
• Slew Rate: 3.3 V/µs
• Gain Bandwidth Product: 1.4MHz
• Current - Input Bias: 2pA
• Voltage - Input Offset: 750µV
• Current - Supply: 165µA
• Current - Output / Channel: 20mA
• Voltage - Supply, Single/dual (±): 8 V ~ 36 V, ±4 V ~ 18 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 16-LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Output Type: -
• -3db Bandwidth: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADA4062-2/ADA4062-4
PHASE REVERSAL
Phase reversal occurs in some amplifiers when the input common-
mode voltage range is exceeded. When the voltage driving the
input to these amplifiers exceeds the maximum input common-
mode voltage range, the output of the amplifiers changes polarity.
Most JFET input amplifiers have phase reversal if either input
exceeds the input common-mode range.
For the ADA4062-x, the output does not phase reverse if one
or both of the inputs exceeds the input voltage range but remains
within the positive supply rail and 0.5 V above the negative
supply rail. In other words, for an application with a supply
voltage of ±15 V, the input voltage can be as high as +15 V
without any output phase reversal. However, when the voltage
of the inputs is driven beyond −14.5 V, phase reversal occurs
due to saturation of the input stage leading to forward biasing
of the gate-drain diode. Phase reversal in ADA4062-x can be
prevented by using a Schottky diode to clamp the input terminals
to each other. In the simple buffer circuit in Figure 63, D1
protects the op amp against phase reversal, and R limits the
input current that flows into the op amp.
Figure 63. Phase Reversal Solution Circuit
10kΩ
R
IN5711
D1
+V
–V
SY
SY
ADA4062-x
V
O
Rev. B | Page 16 of 20
V
IN
V
OUT
Figure 64. No Phase Reversal
TIME (40µs/DIV)
V
SY
= ±15V