ADCLK846BCPZ Analog Devices Inc, ADCLK846BCPZ Datasheet - Page 3

• Manufacturer Part Number: ADCLK846BCPZ
• Description: 1.8V 6LVDS/12 CMOS Clock Fanout Buffer
• Manufacturer: Analog Devices Inc
• Type: Fanout Buffer (Distribution)r

Specifications of ADCLK846BCPZ

• Design Resources: Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers (CN0121)
• Number Of Circuits: 1
• Ratio - Input:output: 1:6
• Differential - Input:output: Yes/Yes
• Input: CML, CMOS, HSTL, LVDS, LVPECL
• Output: CMOS, LVDS
• Frequency - Max: 1.2GHz
• Voltage - Supply: 1.71 V ~ 1.89 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-LFCSP
• Frequency-max: 1.2GHz
• Number Of Outputs: 12
• Operating Supply Voltage (max): 1.89V
• Operating Temp Range: -40C to 85C
• Propagation Delay Time: 4.2ns
• Operating Supply Voltage (min): 1.71V
• Mounting: Surface Mount
• Pin Count: 24
• Operating Supply Voltage (typ): 1.8V
• Package Type: LFCSP EP
• Input Frequency: 1.2GHz
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
Typical values are given for V
V
Table 1.
Parameter
CLOCK INPUTS
LVDS CLOCK OUTPUTS
CMOS CLOCK OUTPUTS
S
Input Frequency
Input Sensitivity, Differential
Input Level
Input Common-Mode Voltage
Input Common-Mode Range
Input Voltage Offset
Input Sensitivity, Single-Ended
Input Resistance (Differential)
Input Capacitance
Input Bias Current (Each Pin)
Output Frequency
Differential Output Voltage
Offset Voltage
Short-Circuit Current
Output Frequency
Output Voltage High
Output Voltage Low
Reference Voltage
Output Voltage
Output Resistance
Output Current
= 1.8 V ± 5% and T
A
= −40°C to +85°C variations, unless otherwise noted. Input slew rate > 1 V/ns, unless otherwise noted.
S
= 1.8 V and T
Symbol
V
V
V
C
V
ΔV
V
ΔV
I
V
V
S
CM
CMR
IN
OD
OS
A, I
OH
OL
REF
OD
OS
S
B
A
Min
0
V
0.4
−350
247
1.125
V
V
V
= 25°C, unless otherwise noted. Minimum and maximum values are given over the full
S
S
S
S
/2 − 0.1
/2 − 0.1
− 0.1
− 0.35
Typ
150
30
150
7
2
344
1.25
3
V
60
S
/2
Rev. B | Page 3 of 16
Max
1200
1.8
V
V
+350
1200
454
50
1.375
50
6
250
0.1
0.35
V
500
S
S
S
/2 + 0.05
/2 + 0.1
− 0.4
Unit
MHz
mV p-p
V p-p
V
V
mV
mV p-p
kΩ
pF
μA
MHz
mV
mV
V
mV
mA
MHz
V
V
V
V
V
Ω
μA
Conditions
Differential input
Jitter performance is improved with higher slew
rates (greater voltage swing)
Larger voltage swings can turn on the protection
diodes and can degrade jitter performance
Inputs are self-biased; enables ac coupling
Inputs are dc-coupled with 200 mV p-p signal
applied
CLK ac-coupled; CLK ac-bypassed to ground
Full input swing
Termination = 100 Ω; differential (OUTx, OUTx)
See Figure 9 for a swing vs. frequency plot
Each pin (output shorted to GND )
Single-ended; termination = open
OUTx and OUTx in phase
With 10 pF load each output; see Figure 16 for
swing vs. frequency
At 1 mA load
At 10 mA load
At 1 mA load
At 10 mA load
±500 μA
ADCLK846