ADCLK854/PCBZ Analog Devices Inc, ADCLK854/PCBZ Datasheet - Page 4

• Manufacturer Part Number: ADCLK854/PCBZ
• Description: Evaluation Kit For 1.8v 6vvds/12 CMOS Cl
• Manufacturer: Analog Devices Inc

Specifications of ADCLK854/PCBZ

• Design Resources: Clock Distribution Circuit with Pin-Programmable Output Frequency, Output Logic Levels, and Fanout (CN0152)
• Main Purpose: Timing, Clock Buffer / Driver / Receiver / Translator
• Embedded: No
• Utilized Ic / Part: ADCLK854
• Primary Attributes: 2 Inputs, 12 Outputs
• Secondary Attributes: CMOS, LVDS Outputs
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADCLK854
TIMING CHARACTERISTICS
Table 2. Timing Characteristics
Parameter
LVDS OUTPUTS
CMOS OUTPUTS
LVDS-TO-CMOS OUTPUT SKEW
1
2
3
This is the difference between any two similar delay paths while operating at the same voltage and temperature.
Calculated from the SNR of the ADC method.
Measured at the rising edge of the clock signal.
LVDS Output(s) and CMOS Output(s) on the
Output Rise/Fall Time
Propagation Delay, Clock-to-LVDS Output
Output Skew
Additive Time Jitter
Output Rise/Fall Time
Propagation Delay, Clock-to-CMOS Output
Output Skew
Additive Time Jitter
Integrated Random Jitter
Same Part
LVDS Outputs in the Same Bank
All LVDS Outputs
Integrated Random Jitter
Broadband Random Jitter
Crosstalk Induced Jitter
Temperature Coefficient
CMOS Outputs in the Same Bank
All CMOS Outputs
Broadband Random Jitter
Crosstalk Induced Jitter
Temperature Coefficient
On the Same Part
Across Multiple Parts
On the Same Part
Across Multiple Parts
1
1
2
2
3
Symbol
t
t
t
t
R
PD
R,
PD
, t
t
F
F
Rev. 0 | Page 4 of 16
Min
1.5
2.5
0.8
Typ
135
2.0
2.0
54
74
86
150
260
525
3.2
2.2
56
100
260
Max
235
2.7
50
65
390
950
4.2
155
175
640
1.6
Unit
ps
ps/°C
fs rms
fs rms
ns
fs rms
fs rms
ns
ps
ps
ps
fs rms
fs rms
fs rms
ps
ps/°C
ps
ps
ps
fs rms
ns
Conditions
Termination = 100 Ω differential; 3.5 mA
20% to 80% measured differentially
V
BW = 12 kHz to 20 MHz; clock = 1000 MHz
BW = 50 kHz to 80 MHz; clock = 1000 MHz
BW = 10Hz to 100 MHz; clock = 1000 MHz
Input slew = 1 V/ns, see Figure 11
Calculated from spur energy with an
interferer 10 MHz offset from the carrier
20% to 80%; C
10 pF load
BW = 12 kHz to 20 MHz; clock = 200 MHz
Input slew = 2 V/ns, see Figure 11
Calculated from spur energy with an
interferer 10 MHz offset from the carrier
CMOS load = 10 pF and LVDS load = 100 Ω
ICM
= V
REF
, V
ID
LOAD
= 0.5 V
= 10 pF