ADE5566ASTZF62-RL Analog Devices Inc, ADE5566ASTZF62-RL Datasheet
ADE5566ASTZF62-RL
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ADE5566ASTZF62-RL Summary of contents
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GENERAL FEATURES Wide supply voltage operation: 2 3.7 V Internal bipolar switch between regulated and battery inputs Ultralow power operation with power saving modes (PSM) Full operation: 4 1.6 mA (PLL clock dependent) Battery mode: 3.3 ...
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ADE5166/ADE5169/ADE5566/ADE5569 TABLE OF CONTENTS General Features ............................................................................... 1 Energy Measurement Features ........................................................ 1 Microprocessor Features .................................................................. 1 Revision History ............................................................................... 3 General Description ......................................................................... 4 Functional Block Diagrams ............................................................. 4 Specifications ..................................................................................... 6 Energy Metering ........................................................................... 6 Analog Peripherals ....................................................................... ...
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Writing to the Watchdog Timer SFR (WDCON, Address 0xC0) ............................................................................................. 98 Watchdog Timer Interrupt......................................................... 98 LCD Driver ...................................................................................... 99 LCD Registers .............................................................................. 99 LCD Setup ................................................................................. 102 LCD Timing and Waveforms ................................................. 102 Blink Mode ................................................................................ 103 Scrolling Mode ......................................................................... ...
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ADE5166/ADE5169/ADE5566/ADE5569 GENERAL DESCRIPTION The ADE5166/ADE5169/ADE5566/ADE5569 Analog Devices, Inc., energy (ADE) metering IC analog front end and fixed function DSP solution with an enhanced 8052 MCU core, a full RTC, an LCD driver, and all the peripherals to make an electronic ...
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SPI/I SERIAL INTERFACE 1.20V REF + PGA1 ADC – ENERGY MEASUREMENT DSP + ADC PGA2 – PROGRAM MEMORY 62kB FLASH DGND ...
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ADE5166/ADE5169/ADE5566/ADE5569 SPECIFICATIONS V = 3.3 V ± 5%, AGND = DGND = 0 V, on-chip reference XTALx = 32.768 kHz ENERGY METERING Table 2. Parameter 1 MEASUREMENT ACCURACY Phase Error Between Channels PF = 0.8 Capacitive PF = ...
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ANALOG PERIPHERALS Table 3. Parameter INTERNAL ADCs (BATTERY, TEMPERATURE, V Power Supply Operating Range 1 No Missing Codes 2 Conversion Delay ADC Gain V Measurement DCIN V Measurement BAT Temperature Measurement ADC Offset V Measurement DCIN V ...
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ADE5166/ADE5169/ADE5566/ADE5569 Parameter LCD, RESISTOR LADDER ACTIVE Leakage Current V1 Segment Line Voltage V2 Segment Line Voltage V3 Segment Line Voltage ON-CHIP REFERENCE Reference Error Power Supply Rejection Temperature Coefficient 1 1 These specifications are not production tested but are guaranteed ...
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Parameter POWER SUPPLY INPUTS BAT INTERNAL POWER SUPPLY SWITCH (V SWOUT Resistance BAT SWOUT Resistance DD SWOUT V to/from V Switching Open Time BAT DD BCTRL State Change and ...
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ADE5166/ADE5169/ADE5566/ADE5569 TIMING SPECIFICATIONS AC inputs during testing were driven at V and at 0.45 V for Logic 0. Timing measurements were made at V minimum for Logic 1 and at V maximum for Logic 0, as shown in IL Figure ...
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Table 7. SPI Master Mode Timing Parameters (SPICPHA = 1) Parameter Description t SCLK low pulse width SL t SCLK high pulse width SH t Data output valid after SCLK edge DAV t Data input setup time before SCLK edge ...
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ADE5166/ADE5169/ADE5566/ADE5569 Table 8. SPI Master Mode Timing Parameters (SPICPHA = 0) Parameter Description t SCLK low pulse width SL t SCLK high pulse width SH t Data output valid after SCLK edge DAV t Data output setup before SCLK edge ...
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Table 9. SPI Slave Mode Timing Parameters (SPICPHA = 1) Parameter Description SCLK edge SS t SCLK low pulse width SL t SCLK high pulse width SH t Data output valid after SCLK edge DAV t Data ...
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ADE5166/ADE5169/ADE5566/ADE5569 Table 10. SPI Slave Mode Timing Parameters (SPICPHA = 0) Parameter Description SCLK edge SS t SCLK low pulse width SL t SCLK high pulse width SH t Data output valid after SCLK edge DAV t ...
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ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. A Table 11. Parameter V to DGND DGND BAT V to DGND DCIN Input LCD Voltage to AGND, LCDVA, 1 LCDVB, LCDVC Analog Input Voltage to AGND, V ...
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ADE5166/ADE5169/ADE5566/ADE5569 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS COM3/FP27 COM2/FP28 COM1 COM0 P1.2/FP25/ZX P1.3/T2EX/FP24 P1.4/T2/FP23 P1.5/FP22 P1.6/FP21 P1.7/FP20 P0.1/FP19 P2.0/FP18 P2.1/FP17 P2.2/FP16 LCDVC LCDVP2 Table 13. Pin Function Descriptions Pin No. Mnemonic Description 1 COM3/FP27 Common Output 3/LCD Segment Output 27. COM3 ...
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Pin No. Mnemonic Description 42 P0.3/CF2 General-Purpose Digital I/O Port 0.3/Calibration Frequency Logic Output 2. The CF2 logic output gives instantaneous active, reactive, or apparent power P0.2/CF1 General-Purpose Digital I/O Port 0.2/Calibration Frequency Logic Output 1. The ...
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ADE5166/ADE5169/ADE5566/ADE5569 COM3/FP27 COM2/FP28 COM1 COM0 P1.2/FP25/ZX P1.3/T2EX/FP24 P1.4/T2/FP23 P1.5/FP22 P1.6/FP21 P1.7/FP20 P0.1/FP19 P2.0/FP18 P2.1/FP17 P2.2/FP16 LCDVC LCDVP2 Table 14. Pin Function Descriptions Pin No. Mnemonic Description 1 COM3/FP27 Common Output 3/LCD Segment Output 27. COM3 is used for the LCD ...
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Pin No. Mnemonic Description 43 P0.2/CF1 General-Purpose Digital I/O Port 0.2/Calibration Frequency Logic Output 1. The CF1 logic output gives instantaneous active, reactive, or apparent power SDEN/P2.3/TxD2 Serial Download Mode Enable/General-Purpose Digital Output Port 2.3/Transmitter Data Output ...
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ADE5166/ADE5169/ADE5566/ADE5569 TYPICAL PERFORMANCE CHARACTERISTICS 2.0 MID CLASS C GAIN = 1 1.5 INTEGRATOR OFF INTERNAL REFERENCE 1.0 0.5 +25° +85° –40° –0.5 –1.0 –1.5 MID CLASS C –2.0 0.1 1 ...
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GAIN = 1 0.4 INTEGRATOR OFF INTERNAL REFERENCE 0.3 0 3.13V RMS 0 3.3V RMS 0 –0 3.43V RMS –0.2 –0.3 –0.4 –0.5 0.1 1 CURRENT CHANNEL (% of Full Scale) Figure 17. ...
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ADE5166/ADE5169/ADE5566/ADE5569 2.0 MID CLASS C GAIN = 16 INTEGRATOR OFF 1.5 INTERNAL REFERENCE 1.0 0.5 ; +25° +85° –0.5 –40° –1.0 –1.5 MID CLASS C –2.0 0.1 1 CURRENT CHANNEL (% of ...
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MID CLASS C GAIN = 16 INTEGRATOR ON 1.5 INTERNAL REFERENCE 1.0 ; –40° 0.5 ; +85° +85° –40° 0.5 –0.5 +25° +25° 0.5 ...
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ADE5166/ADE5169/ADE5566/ADE5569 TERMINOLOGY Measurement Error The error associated with the energy measurement made by the ADE5166/ADE5169/ADE5566/ADE5569 is defined by the fol- lowing formula: Measurement Error = ⎛ ⎞ − Energy Register True Energy ⎜ ⎟ ⎜ ⎟ True Energy ⎝ ⎠ ...
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SPECIAL FUNCTION REGISTER (SFR) MAPPING Table 15. SFR Mapping Mnemonic Address Description INTPR 0xFF Interrupt pins configuration SFR (see Table 17). SCRATCH4 0xFE Scratch Pad 4 (see Table 25). SCRATCH3 0xFD Scratch Pad 3 (see Table 24). SCRATCH2 0xFC Scratch ...
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ADE5166/ADE5169/ADE5566/ADE5569 Mnemonic Address Description SBAUDT 0x9E Enhanced serial baud rate control (see Table 142). SBAUDF 0x9D UART timer fractional divider (see Table 143). LCDCONX 0x9C LCD Configuration X (see Table 92). 2 SPI2CRx 0x9B SPI/I C receive buffer (see Table ...
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POWER MANAGEMENT The ADE5166/ADE5169/ADE5566/ADE5569 have elaborate power management circuitry that manages the regular power supply to battery switchover and power supply failures. Table 16. Power Management SFRs SFR Address R/W Mnemonic 0xEC R/W IPSME 0xF5 R/W BATPR 0xF8 R/W IPSMF ...
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ADE5166/ADE5169/ADE5566/ADE5569 Table 18. Power Management Interrupt Flag SFR (IPSMF, Address 0xF8) Bit Bit Address Mnemonic Default 7 0xFF FPSR 0 6 0xFE FPSM 0 5 0xFD FSAG 0 4 0xFC Reserved 0 3 0xFB FVADC 0 2 0xFA FBAT 0 ...
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Table 22. Scratch Pad 1 SFR (SCRATCH1, Address 0xFB) Bit Mnemonic Default Description [7:0] SCRATCH1 0 Value can be written/read in this register. This value is maintained in all the power saving modes. Table 23. Scratch Pad 2 SFR (SCRATCH2, ...
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ADE5166/ADE5169/ADE5566/ADE5569 POWER SUPPLY ARCHITECTURE The ADE5166/ADE5169/ADE5566/ADE5569 have two power supply inputs, V and V . They require only a single 3.3 V power DD BAT supply at V for full operation. A battery backup, or secondary DD power supply, with ...
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EPSR FPSR ESAG FSAG EVADC FVADC EBAT FBAT EBSO FBSO EVDCIN FVDCIN IPSME ADDR. 0xEC EPSR IPSMF ADDR. 0xF8 FPSR IEIP2 ADDR. 0xA9 PS2 NOT INVOLVED IN PSM INTERRUPT SIGNAL CHAIN Battery Switchover and Power Supply Restored PSM Interrupt The ...
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ADE5166/ADE5169/ADE5566/ADE5569 SAG Monitor PSM Interrupt The ADE5166/ADE5169/ADE5566/ADE5569 energy measure- ment DSP monitors the ac voltage input at the V pins. The SAGLVL register (Address 0x14) is used to set the thresh- old for a line voltage SAG event. The FSAG ...
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V – SAG LEVEL TRIP POINT SAGCYC = 1 V DCIN 1. 2.75V Figure 35. Power Supply Management Interrupts and Battery Switchover with Only V V – SAG LEVEL TRIP POINT SAGCYC ...
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ADE5166/ADE5169/ADE5566/ADE5569 V − SAG LEVEL TRIP POINT V DCIN 1.2V V BAT V DD 2.75V V SWOUT BATTERY SWITCH ENABLED ON LOW V DCIN V SWOUT BATTERY SWITCH ENABLED ON LOW EVENT SAG EVENT ...
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OPERATING MODES PSM0 (NORMAL MODE) In PSM0 mode, or normal operating mode All of the analog circuitry and digital circuitry powered and V are enabled by default. In normal mode, the INTD INTA default ...
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ADE5166/ADE5169/ADE5566/ADE5569 3.3 V PERIPHERALS AND WAKE-UP EVENTS Some of the 3.3 V peripherals are capable of waking the ADE5166/ ADE5169/ADE5566/ADE5569 from PSM2 mode. The events that can cause the ADE5166/ADE5169/ADE5566/ADE5569 to wake up from PSM2 mode are listed in the ...
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TRANSITIONING BETWEEN OPERATING MODES The operating mode of the ADE5166/ADE5169/ADE5566/ ADE5569 is determined by the power supply connected Therefore, changes in the power supply, such as when SWOUT V switches from when V ...
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ADE5166/ADE5169/ADE5566/ADE5569 ENERGY MEASUREMENT The ADE5166/ADE5169/ADE5566/ADE5569 offer a fixed func- tion, energy measurement, digital processing core that provides all the information needed to measure energy in single-phase energy meters. The part provides two ways to access the energy measurements: direct access ...
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Table 31. Energy Measurement SFRs Address R/W Mnemonic 0x91 R/W MADDPT 0x92 R/W MDATL 0x93 R/W MDATM 0x94 R/W MDATH 0xD1 R VRMSL 0xD2 R VRMSM 0xD3 R VRMSH 0xD4 R IRMSL 0xD5 R IRMSM 0xD6 R IRMSH 0xD9 R/W ...
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ADE5166/ADE5169/ADE5566/ADE5569 ×1, ×2, ×4, ×8, ×16 {GAIN[2:0 PGA1 I ADC HPF I N PHCAL[7: PGA2 ADC V N INTEGRATOR WGAIN[11:0] MULTIPLIER dt LPF2 WATTOS[15:0] π VARGAIN[11:0] 2 Ф LPF2 VAROS[15:0] IRMSOS[11:0] VAGAIN[11:0] × 2 LPF VRMSOS[11:0] ...
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ENERGY MEASUREMENT REGISTERS Table 32. Energy Measurement Register List Address Length MADDPT[6:0] Mnemonic R/W (Bits) 0x01 WATTHR R 24 0x02 RWATTHR R 24 0x03 LWATTHR 0x04 VARHR 0x05 RVARHR 0x06 LVARHR ...
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ADE5166/ADE5169/ADE5566/ADE5569 Address Length MADDPT[6:0] Mnemonic R/W (Bits) 0x29 CF2NUM R/W 16 0x2A CF2DEN R/W 16 0x2B MODE3 R/W 8 0x3B Reserved 0x3C Reserved 0x3D CALMODE 2 R/W 8 0x3E Reserved 0x3F Reserved 1 This function is not available in the ...
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Table 35. Waveform Mode Register (WAVMODE, Address 0x0D) Bit Mnemonic Default [7:5] WAV2SEL 000 [4:2] WAV1SEL 000 [1:0] DTRT 00 1 This function is not available in the ADE5166 and ADE5566. Table 36. No Load Configuration Register (NLMODE, Address 0x0E) ...
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ADE5166/ADE5169/ADE5566/ADE5569 Table 37. Accumulation Mode Register (ACCMODE, Address 0x0F) Bit Mnemonic Default 1 7 ICHANNEL FAULTSIGN VARSIGN 0 4 APSIGN ABSVARM SAVARM 0 1 POAM 0 0 ABSAM ...
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Table 40. Calibration Mode Register (CALMODE, Address 0x3D) Bit Mnemonic Default [7:6] Reserved 00 [5:4] SEL_I_CH 00 3 V_CH_SHORT 0 2 I_CH_SHORT 0 [1:0] Reserved 00 1 This register is not available in the ADE5566 and ADE5569. INTERRUPT STATUS/ENABLE SFRS ...
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ADE5166/ADE5169/ADE5566/ADE5569 Table 44. Interrupt Enable 1 SFR (MIRQENL, Address 0xD9) Bit Interrupt Enable Bit Description [7:6] Reserved Reserved FAULTSIGN When this bit is set to Logic 1, the FAULTSIGN flag set creates a pending ADE interrupt to the ...
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ANALOG-TO-DIGITAL CONVERSION Each ADE5166/ADE5169/ADE5566/ADE5569 has two Σ-Δ analog-to-digital converters (ADCs). The outputs of these ADCs are mapped directly to waveform sampling SFRs (Address 0xE2 to Address 0xE7) and are used for energy measurement internal digital signal processing. In PSM1 (battery) ...
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ADE5166/ADE5169/ADE5566/ADE5569 Antialiasing Filter Figure 44 also shows an analog LPF (RC) on the input to the modulator. This filter is present to prevent aliasing, an artifact of all sampled systems. Aliasing means that frequency components in the input signal to ...
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REFERENCE {GAIN[2:0 PGA1 PGA1 0.25V, 0.125V, 62.5mV, 31.3mV 0V ANALOG INPUT RANGE *WHEN THE DIGITAL INTEGRATOR IS ENABLED, FULL-SCALE OUTPUT DATA IS ATTENUATED DEPENDING ON THE SIGNAL ...
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ADE5166/ADE5169/ADE5566/ADE5569 Voltage Channel ADC Figure 48 shows the ADC and signal processing chain for the voltage channel. In waveform sampling mode, the ADC outputs a signed, twos complement, 24-bit data-word at a maximum of 25.6 kSPS (MCLK/160). The ADC produces ...
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FAULT DETECTION (ADE5166/ADE5169 ONLY) The ADE5166/ADE5169 incorporate a fault detection scheme that warns of fault conditions and allows accurate measurement to continue during a fault event. (This feature is not available in the ADE5566/ADE5569.) The ADE5166/ADE5169 do this by con- ...
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ADE5166/ADE5169/ADE5566/ADE5569 For calibration, a first measurement should be done on I setting the SEL_I_CH bits (Bits[5:4]) to 0b01 in the CALMODE register (Address 0x3D). This measurement should be compared to the measurement Measuring the ...
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FREQUENCY (Hz) Figure 54. Combined Phase Response of the Digital Integrator and Phase Compensator ( Hz) Note that the integrator has a −20 dB/dec attenuation ...
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ADE5166/ADE5169/ADE5566/ADE5569 Figure 56 shows the mechanism of the zero-crossing timeout detection when the line voltage stays at a fixed dc level for more than MCLK/160 × ZXTOUT seconds. 12-BIT INTERNAL REGISTER VALUE ZXTOUT VOLTAGE CHANNEL ZXTO FLAG BIT Figure 56. ...
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Peak Detection The ADE5166/ADE5169/ADE5566/ADE5569 can be program- med to detect when the absolute value of the voltage or current channel exceeds a specified peak value. Figure 58 illustrates the behavior of the peak detection for the voltage channel. Both voltage ...
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ADE5166/ADE5169/ADE5566/ADE5569 Figure 59 illustrates how the phase compensation is used to remove a 0.1° phase lead in the current channel due to the external transducer. To cancel the lead (0.1°) in the current channel, a phase lead must also be ...
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One LSB of the current channel rms offset is equivalent to 16,384 LSBs of the square of the current channel rms register. Assuming that the maximum value from the current channel rms calculation is 0d1,898,124 with full-scale ac inputs, then ...
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ADE5166/ADE5169/ADE5566/ADE5569 VOLTAGE CHANNEL Voltage Channel RMS Calculation Figure 63 shows details of the signal processing chain for the rms calculation on the voltage channel. This voltage rms estimation is done in the ADE5166/ADE5169/ADE5566/ADE5569 using the mean absolute value calculation, as ...
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Note that the active power is equal to the dc component of the instantaneous power signal, P(t), in Equation 9, that is, VI. This is the relationship used to calculate active power in the ADE5166/ ADE5169/ADE5566/ADE5569. The instantaneous power signal, ...
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ADE5166/ADE5169/ADE5566/ADE5569 Active Power Gain Calibration Figure 66 shows the signal processing chain for the active power calculation in the ADE5166/ADE5169/ADE5566/ADE5569. As explained previously, the active power is calculated by filtering the output of the multiplier with a low-pass filter. Note ...
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ACTIVE ENERGY CALCULATION As stated in the Active Power Calculation section, active power is defined as the rate of energy flow. This relationship can be expressed mathematically, as shown in Equation 11 where power. ...
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ADE5166/ADE5169/ADE5566/ADE5569 Figure 67 shows this energy accumulation for full-scale signals (sinusoidal) on the analog inputs. The three displayed curves illustrate the minimum period of time it takes the energy register to roll over when the active power gain register contents ...
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ACTIVE ENERGY NO LOAD THRESHOLD ACTIVE POWER NO LOAD THRESHOLD APSIGN FLAG APNOLOAD POS INTERRUPT STATUS REGISTERS Figure 69. Energy Accumulation in Absolute Accumulation Mode Active Energy Pulse Output All of the ADE5166/ADE5169/ADE5566/ADE5569 circuitry has a pulse output whose frequency ...
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ADE5166/ADE5169/ADE5566/ADE5569 When a new half-line cycle is written in the LINCYC register (Address 0x12), the LWATTHR register (Address 0x03) is reset, and a new accumulation starts at the next zero crossing. The number of half-line cycles is then counted until ...
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Reactive Power Gain Calibration Figure 72 shows the signal processing chain for the ADE5169/ ADE5569 reactive power calculation. As explained in the Reactive Power Calculation (ADE5169/ADE5569) section, the reactive power is calculated by applying a low-pass filter to the instanta- ...
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ADE5166/ADE5169/ADE5566/ADE5569 REACTIVE ENERGY CALCULATION (ADE5169/ADE5569 ONLY) As for active energy, the ADE5169/ADE5569 achieve the integra- tion of the reactive power signal by continuously accumulating the reactive power signal in an internal, nonreadable, 49-bit energy register. The reactive energy register (VARHR, ...
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Integration Time Under Steady Load—Reactive Energy As mentioned in the Active Energy Calculation section, the discrete time sample period (T) for the accumulation register is 1.22 μs (5/MCLK). With full-scale sinusoidal signals on the analog inputs, and with the VARGAIN ...
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ADE5166/ADE5169/ADE5566/ADE5569 Line Cycle Reactive Energy Accumulation Mode In line cycle reactive energy accumulation mode, the energy accumulation of the ADE5169/ADE5569 can be synchronized to the voltage channel zero crossing so that reactive energy can be accumulated over an integral number ...
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APPARENT POWER CALCULATION Apparent power is defined as the maximum power that can be delivered to a load. V and I are the effective voltage and current rms rms delivered to the load, respectively. Therefore, the apparent power (AP) = ...
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ADE5166/ADE5169/ADE5566/ADE5569 Figure 77 shows this discrete time integration or accumulation. The apparent power signal is continuously added to the internal register. This addition is a signed addition even if the apparent energy theoretically remains positive. The 49 bits of the ...
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Line Cycle Apparent Energy Accumulation Mode The ADE5166/ADE5169/ADE5566/ADE5569 are designed with a special apparent energy accumulation mode that simplifies the calibration process. By using the on-chip, zero-crossing detection, the ADE5166/ADE5169/ADE5566/ADE5569 accumulate the apparent power signal in the LVAHR register (Address ...
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ADE5166/ADE5169/ADE5566/ADE5569 ENERGY-TO-FREQUENCY CONVERSION The ADE5166/ADE5169/ADE5566/ADE5569 also provide two energy-to-frequency conversions for calibration purposes. After initial calibration at manufacturing, the manufacturer or end customer often verifies the energy meter calibration. One conve- nient way to do this is for the manufacturer ...
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ENERGY MEASUREMENT INTERRUPTS The energy measurement part of the ADE5166/ADE5169/ ADE5566/ADE5569 has its own interrupt vector for the 8052 core, Vector Address 0x004B (see the Interrupt Vectors section). The bits set in the Interrupt Enable 1 SFR (MIRQENL, Address 0xD9), ...
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ADE5166/ADE5169/ADE5566/ADE5569 TEMPERATURE, BATTERY, AND SUPPLY VOLTAGE MEASUREMENTS The ADE5166/ADE5169/ADE5566/ADE5569 include tem- perature measurements as well as battery and supply voltage measurements. These measurements enable many forms of compensation. The temperature and supply voltage measurements can be used to compensate external ...
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Table 51. Temperature and Supply Delta SFR (DIFFPROG, Address 0xF3) Bit Mnemonic Default Description [7:6] Reserved 00 Reserved. [5:3] TEMP_DIFF 00 Difference threshold between last temperature measurement interrupting 8052 and new temperature measurement that should interrupt 8052. TEMP_DIFF 000 001 ...
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ADE5166/ADE5169/ADE5566/ADE5569 TEMPERATURE MEASUREMENT To provide a digital temperature measurement, each ADE5166/ ADE5169/ADE5566/ADE5569 includes a dedicated ADC. The 8-bit temperature ADC value SFR (TEMPADC, Address 0xD7) holds the results of the temperature conversion. The resolution of the temperature measurement is 0.83°C/LSB. ...
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This method allows battery measurement to take place completely in the background, requiring MCU activity only if the battery drops below a user-specified threshold. To set up background battery measurements, follow these steps: 1. Configure the battery detection threshold SFR ...
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ADE5166/ADE5169/ADE5566/ADE5569 External Voltage ADC in PSM1 and PSM2 Modes An external voltage conversion is initiated only by certain actions that depend on the operating mode of the ADE5166/ADE5169/ ADE5566/ADE5569. • In PSM0 operating mode, the 8052 is active. External voltage ...
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MCU CORE ARCHITECTURE The ADE5166/ADE5169/ADE5566/ADE5569 have an 8052 MCU core and use the 8051 instruction set. Some of the standard 8052 peripherals, such as the UART, have been enhanced. This section describes the standard 8052 core and enhancements that ...
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ADE5166/ADE5169/ADE5566/ADE5569 Table 59. Program Control SFR (PCON, Address 0x87) Bit Mnemonic Default Description 7 SMOD 0 Double baud rate control. [6:0] Reserved 0 Reserved. These bits must be kept at 0 for proper operation. Table 60. Data Pointer Low SFR ...
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Bit Mnemonic Default Description 4 MOD38EN 0 38 kHz modulation enable bit. MOD38EN 0 1 [3:2] Reserved 00 Reserved. These bits should be kept at 0 for proper operation. [1:0] XREN1, 01 XREN1, XREN0 XREN0 XREN1 or XREN0 = 1 ...
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ADE5166/ADE5169/ADE5566/ADE5569 The stack resides in the upper part of the extended internal RAM. The SP bits in the stack pointer SFR (SP, Address 0x81[7:0]) and the SP bits in the stack pointer high SFR (SPH, Address 0xB7[2:0]) hold the address ...
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A useful implementation of the waterline feature is to determine the amount of space required for the stack and allow a suitable default starting address to be selected. This optimizes the use of the additional XRAM space, allowing it to ...
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ADE5166/ADE5169/ADE5566/ADE5569 MEMORY OVERVIEW The ADE5166/ADE5169/ADE5566/ADE5569 contain three memory blocks, as follows: • on-chip Flash/EE program and data memory • 256 bytes of general-purpose RAM • extended internal RAM (XRAM) The 256 bytes of general-purpose ...
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Code Memory Code and data memory is stored in the 62 kB flash memory space. No external code memory is supported. To access code memory, code indirect addressing is used. ADDRESSING MODES The 8052 core provides several addressing modes. The ...
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ADE5166/ADE5169/ADE5566/ADE5569 Code Indirect Addressing The internal code memory can be accessed indirectly. This can be useful for implementing lookup tables and other arrays of constants that are stored in flash memory. For example, to move the data stored in flash ...
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Mnemonic Description XRL A, dir Exclusive-OR indirect memory to A XRL dir, #data Exclusive-OR immediate data to direct CLR A Clear A CPL A Complement A SWAP A Swap nibbles Rotate A left RLC A Rotate ...
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ADE5166/ADE5169/ADE5566/ADE5569 Mnemonic Description Branching JMP @A+DPTR Jump indirect relative to DPTR RET Return from subroutine RETI Return from interrupt ACALL addr11 Absolute jump to subroutine AJMP addr11 Absolute jump unconditional SJMP rel Short jump (relative address) JC rel Jump on ...
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INSTRUCTIONS THAT AFFECT FLAGS Many instructions explicitly modify the carry bit, such as the MOV C bit and CLR C instructions. Other instructions that affect status flags are listed in this section. ADD A, Source This instruction adds the source ...
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ADE5166/ADE5169/ADE5566/ADE5569 RLC A This instruction rotates the accumulator to the left through the carry flag. The old MSB of the accumulator becomes the new carry flag, and the old carry flag is loaded into the new LSB of the accumulator. ...
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DUAL DATA POINTERS Each ADE5166/ADE5169/ADE5566/ADE5569 incorporates two data pointers. The second data pointer is a shadow data pointer and is selected via the data pointer control SFR (DPCON, Address 0xA7). DPCON features automatic hardware post- increment and postdecrement, as well ...
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ADE5166/ADE5169/ADE5566/ADE5569 INTERRUPT SYSTEM The unique power management architecture of the ADE5166/ ADE5169/ADE5566/ADE5569 includes an operating mode (PSM2) where the 8052 MCU core is shut down. Events can be configured to wake the 8052 MCU core from the PSM2 operating mode. ...
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Table 82. Interrupt Priority SFR (IP, Address 0xB8) Bit Bit Address Mnemonic 7 0xBF PADE 6 0xBE PTEMP 5 0xBD PT2 4 0xBC PS 3 0xBB PT1 2 0xBA PX1 1 0xB9 PT0 0 0xB8 PX0 Table 83. Interrupt Enable ...
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ADE5166/ADE5169/ADE5566/ADE5569 INTERRUPT FLAGS The interrupt flags and status flags associated with the interrupt vectors are shown in Table 85 and Table 86, respectively. Most of the interrupts have flags associated with them. Table 85. Interrupt Flags Interrupt Source Flag IE0 ...
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IPSMF FPSM PSM (IPSMF[6]) IPSME INTERVAL RTC ALARM MIRQSTH MIRQSTM MIRQSTL ADE MIRQENH MIRQENM MIRQENL WATCHDOG TIMEOUT WATCHDOG WDIR TEMPADC INTERRUPT TEMP ADC IT0 0 INT0 EXTERNAL INTERRUPT 0 1 IT0 TF0 TIMER 0 IT1 0 EXTERNAL INT1 INTERRUPT 1 ...
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ADE5166/ADE5169/ADE5566/ADE5569 INTERRUPT VECTORS When an interrupt occurs, the program counter is pushed onto the stack, and the corresponding interrupt vector address is loaded into the program counter. When the interrupt service routine is complete, the program counter is popped off ...
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WATCHDOG TIMER The watchdog timer generates a device reset or interrupt within a reasonable amount of time if the ADE5166/ADE5169/ADE5566/ ADE5569 enter an erroneous state, possibly due to a program- ming error or electrical noise. The watchdog is enabled, by ...
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ADE5166/ADE5169/ADE5566/ADE5569 Table 89. Watchdog and Flash Protection Byte in Flash (Flash Address = 0xF7FF) Bit Mnemonic Default 7 WDPROT_PROTKY7 1 [6:0] PROTKY 0xFF WRITING TO THE WATCHDOG TIMER SFR (WDCON, ADDRESS 0xC0) Writing data to the WDCON SFR involves a ...
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LCD DRIVER Using shared pins, the LCD module is capable of directly driving an LCD panel of 17 × 4 segments without compromising any ADE5166/ADE5169/ADE5566/ADE5569 functions capable of driving LCDs with 2×, 3×, and 4× multiplexing. The LCD ...
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ADE5166/ADE5169/ADE5566/ADE5569 Table 92. LCD Configuration X SFR (LCDCONX, Address 0x9C) Bit Mnemonic Default 7 Reserved 0 6 EXTRES 0 [5:0] BIASLVL 0 Table 93. LCD Bias Voltage When Contrast Control Is Enabled BIASLVL[ BIASLVL × V ...
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Table 96. LCD Frame Rate Selection for f FD3 FD2 FD1 FD0 f (Hz) LCD 256 170 128 102 85.3 ...
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ADE5166/ADE5169/ADE5566/ADE5569 Table 99. LCD Pointer SFR (LCDPTR, Address 0xAC) Bit Mnemonic Default 7 0 R/W 6 Reserved 0 [5:4] RAM2SCREEN 0 [3:0] ADDRESS 0 Table 100. LCD Data SFR (LCDDAT, Address 0xAE) Bit Mnemonic Default [7:0] LCDDATA 0 Table 101. ...
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BLINK MODE Blink mode is enabled by setting the BLINKEN bit (Bit 5) in the LCD configuration SFR (LCDCON, Address 0x95). This mode is used to alternate between the LCD on state and LCD off state so that the LCD ...
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ADE5166/ADE5169/ADE5566/ADE5569 Writing to LCD Data Registers To update the LCD data memory, first set the LSB of the LCD Configuration Y SFR (LCDCONY, Address 0xB1) to freeze the data being displayed on the LCD while updating it. This operation ensures ...
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Charge Pump Voltage generation through the charge pump requires external capacitors to store charge. The external connections to LCDVA, LCDVB, and LCDVC, as well as to LCDVP1 and LCDVP2, are shown in Figure 90. LCDVC LCDVB CHARGE PUMP AND LCDVA ...
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ADE5166/ADE5169/ADE5566/ADE5569 FLASH MEMORY FLASH MEMORY OVERVIEW Flash memory is a type of nonvolatile memory that is in-circuit programmable. The default, erased state of a byte of flash memory is 0xFF. When a byte of flash memory is programmed, the required ...
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The lower 62 bytes are available to the user for program storage or as nonvolatile data memory. They are segmented into 124 pages of 512 bytes each the user to decide which flash memory pages are ...
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ADE5166/ADE5169/ADE5566/ADE5569 0xDFFF 0xDE00 0xDDFF 0xDC00 0xDBFF 0xDA00 0xD9FF 0xD800 0xF7FF 0xD7FF PAGE 123 0xF600 0xD600 0xF5FF 0xD5FF PAGE 122 READ 0xF400 0xD400 PROTECT 0xF3FF 0xD3FF BIT 30 PAGE 121 0xF200 0xD200 0xF1FF 0xD1FF PAGE 120 0xF000 0xD000 0xEFFF 0xCFFF PAGE ...
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ECON—Flash Control SFR Programming the flash memory is done through the flash control SFR (ECON, Address 0xB9). This SFR allows the user to read, write, erase, or verify the flash memory method of security, a ...
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ADE5166/ADE5169/ADE5566/ADE5569 Flash Functions The following sample 8052 code is provided to demonstrate how to use the the flash functions. For these examples, Flash Memory Byte 0x3C00 is accessed. Write Byte Write 0xF3 into Flash Memory Byte 0x3C00. MOV EDATA, #F3h ...
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Note that after the PROTKY has been activated by a reset, any further changes to the protection require the new 8-bit protection key to be written to the PROTKY SFR prior to issuing the ECON command. The PROTKY SFR is ...
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ADE5166/ADE5169/ADE5566/ADE5569 Enabling Flash Protection by Emulator Commands Another way to set the flash protection bytes is to use the reserved emulator commands available only in download mode. These commands write directly to the SFRs and can be used to duplicate ...
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TIMERS Each ADE5166/ADE5169/ADE5566/ADE5569 has three 16-bit timers/counters: Timer/Counter 0, Timer/Counter 1, and Timer/ Counter 2. The timer/counter hardware is included on chip to relieve the processor core of overhead inherent in implementing timer/counter functionality in software. Each timer/counter con- sists ...
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ADE5166/ADE5169/ADE5566/ADE5569 Table 114. Timer/Counter 0 and Timer/Counter 1 Control SFR (TCON, Address 0x88) Bit Bit Address Mnemonic Default 7 0x8F TF1 0 6 0x8E TR1 0 5 0x8D TF0 0 4 0x8C TR0 0x8B IE1 0 1 ...
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Table 116. Timer 0 High Byte SFR (TH0, Address 0x8C) Bit Mnemonic Default Description [7:0] TH0 0 Timer 0 data high byte. Table 117. Timer 0 Low Byte SFR (TL0, Address 0x8A) Bit Mnemonic Default Description [7:0] TL0 0 Timer ...
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ADE5166/ADE5169/ADE5566/ADE5569 Mode 2 (8-Bit Timer/Counter with Autoreload) Mode 2 configures the timer SFR (TH0, Address 0x8C 8-bit counter (TL0, Address 0x8A) with automatic reload, as shown in Figure 99. Overflow from TL0 not only sets TF0 (Address 0x88[5]) ...
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In either case, if Timer 2 is used to generate the baud rate, the TF2 interrupt flag does not occur. Therefore, Timer 2 interrupts do not occur and do not need to be disabled. In this mode, the EXF2 flag ...
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ADE5166/ADE5169/ADE5566/ADE5569 PLL The ADE5166/ADE5169/ADE5566/ADE5569 are intended for use with a 32.768 kHz watch crystal. A PLL locks onto a multiple of this frequency to provide a stable 4.096 MHz clock for the system. The core can operate at this frequency ...
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REAL-TIME CLOCK (RTC) The ADE5166/ADE5169/ADE5566/ADE5569 have an embedded RTC (see Figure 103). The external 32.768 kHz crystal is used as the clock source for the RTC. Calibration is provided to com- pensate the nominal crystal frequency and for variations in ...
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ADE5166/ADE5169/ADE5566/ADE5569 TEMPERATURE ADC ALSEC_EN ALMIN_EN ALHR_EN ALDAY_EN ALDAT_EN RTC SFRs Table 127. List of RTC SFRs SFR Address Bit Addressable TIMECON 0xA1 No TIMECON2 0xA2 No RTCPTR 0xA3 No RTCDAT 0xA4 No KYREG 0xC1 No RTCCOMP 0xF6 No TEMPCAL 0xF7 ...
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Table 128. RTC Configuration SFR (TIMECON, Address 0xA1) Bit Mnemonic Default Description 7 Reserved N/A Reserved. 6 ALFLAG 0 Alarm flag. This bit is set when the RTC registers match the enabled alarm registers. It can be cleared by the ...
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ADE5166/ADE5169/ADE5566/ADE5569 Table 130. RTC Pointer Address SFR (RTCPTR, Address 0xA3) Bit Mnemonic Default 7 RTCW_RB 0 [6:5] Reserved N/A [4:0] RTC_ADDRESS 0 Table 131. RTC Pointer Data SFR (RTCDAT, Address 0xA4) Bit Mnemonic Default [7:0] RTC_DATA 0 Table 132. RTC ...
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RTC REGISTERS Table 134. RTC Register List Address RTCPTR[4:0] Mnemonic R/W Length 0x00 Reserved N/A N/A 0x01 HTHSEC R/W 8 0x02 SEC R/W 8 0x03 MIN R/W 8 0x04 HOUR R/W 8 0x05 DAY R/W 8 0x06 DATE R/W 8 ...
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ADE5166/ADE5169/ADE5566/ADE5569 Table 135. RTC Calibration Configuration Register (RTC_CAL, Address 0x0F) Bit Mnemonic Default 7 CAL_EN_PSM2 0 6 CAL_EN 0 [5:4] FSEL[1: RTC_P2P3 0 2 RTC_P1P2 0 1 RTC_P0P7 0 0 RTC_P0P5 0 RTC CALENDAR The RTC has a ...
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Table 137. Leap Years—Rollover After 29 Days YEAR Register Estimated Year 0d04 2004 0d08 2008 0d12 2012 0d16 2016 0d20 2020 0d24 2024 0d28 2028 0d32 2032 0d36 2036 0d40 2040 0d44 2044 0d48 2048 0d52 2052 0d56 2056 0d60 ...
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ADE5166/ADE5169/ADE5566/ADE5569 RTC CRYSTAL COMPENSATION The RTC provides registers to compensate for the tolerance of the crystal frequency and its variation over temperature ±248 ppm frequency error can be calibrated out by the RTC circuitry. The compensation is fully ...
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UART SERIAL INTERFACE The ADE5166/ADE5169/ADE5566/ADE5569 UART can be configured in one of four modes. • Shift register with baud rate fixed at f • 8-bit UART with variable baud rate • 9-bit UART with baud rate fixed at f • ...
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ADE5166/ADE5169/ADE5566/ADE5569 Table 141. Serial Port Buffer SFR (SBUF, Address 0x99) Bit Mnemonic [7:0] SBUF Table 142. Enhanced Serial Baud Rate Control SFR (SBAUDT, Address 0x9E) Bit Mnemonic Default 7 OWE [4:3] SBTH 00 ...
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Table 144. Common Baud Rates Using the UART Timer with a 4.096 MHz PLL Clock Ideal Baud CD 115,200 0 115,200 1 57,600 0 57,600 1 38,400 0 38,400 1 38,400 2 19,200 0 19,200 1 19,200 2 19,200 3 ...
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ADE5166/ADE5169/ADE5566/ADE5569 UART OPERATION MODES Mode 0 (Shift Register with Baud Rate Fixed at f Mode 0 is selected when the SM0 and SM1 bits in the serial communications control SFR (SCON, Address 0x98[7:6]) are cleared. In this shift register mode, ...
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To transmit, the eight data bits must be written into the serial port buffer SFR (SBUF, Address 0x99). The ninth bit must be written to TB8 in the serial communications control SFR (SCON, Address 0x98[3]). When transmission is initiated, the ...
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ADE5166/ADE5169/ADE5566/ADE5569 Because Timer 2 has 16-bit autoreload capability, very low baud rates are still possible. Timer 2 is selected as the baud rate generator by setting RCLK and/or TCLK in the Timer/Counter 2 control SFR (T2CON, Address 0xC8[5:4]). The baud ...
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SBAUDF is the fractional divider ratio required to achieve the required baud rate. The appropriate value for SBAUDF can be calculated with the following formula: ⎛ f ⎜ CORE SBAUDF = 64 × ⎜ + × DIV SBTH × 16 ...
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ADE5166/ADE5169/ADE5566/ADE5569 UART2 SERIAL INTERFACE The ADE5166/ADE5169/ADE5566/ADE5569 UART2 is an 8-bit or 9-bit UART with variable baud rate. Variable baud rates are defined by using an internal timer to generate any rate between 300 bauds/sec and 115,200 bauds/sec. The UART2 serial ...
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Bit Mnemonic Default [2:0] DIV2 000 Table 149. Common Baud Rates Using the UART2 Timer with a 4.096 MHz PLL Clock Ideal Baud CD SBTH2 115,200 0 0 115,200 1 0 57,600 0 0 57,600 1 0 38,400 0 0 ...
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ADE5166/ADE5169/ADE5566/ADE5569 UART2 OPERATION MODES The UART2 has two operation modes in which each data byte (LSB first) is preceded by a start bit (0), followed by a stop bit (1). Therefore, each frame consists of 10 bits transmitted on the ...
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For example, to get a baud rate of 9600 while operating at a core clock frequency of 4.096 MHz, with the PLL CD bits (POWCON[2:0]) equal to 0 DIV2 + SBTH2 = log(4,096,000/(16 × 9600))/log2 = 4. Note ...
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ADE5166/ADE5169/ADE5566/ADE5569 SERIAL PERIPHERAL INTERFACE (SPI) The ADE5166/ADE5169/ADE5566/ADE5569 integrate a complete hardware serial peripheral interface on chip. The SPI is full duplex so that eight bits of data are synchronously transmitted and simul- taneously received. This SPI implementation is double buffered, ...
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Table 153. SPI Configuration SFR 1 (SPIMOD1, Address 0xE8) Bit Bit Address Mnemonic [7:6] 0xEF to 0xEE Reserved 5 0xED INTMOD 4 0xEC AUTO_SS 3 0xEB SS_EN 2 0xEA RxOFW [1:0] 0xE9 to 0xE8 SPIR ADE5166/ADE5169/ADE5566/ADE5569 Default Description 00 Reserved. ...
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ADE5166/ADE5169/ADE5566/ADE5569 Table 154. SPI Configuration SFR 2 (SPIMOD2, Address 0xE9) Bit Mnemonic Default Description 7 SPICONT 0 Master mode, SPI continuous transfer mode enable bit. SPICONT SPIEN 0 SPI interface enable bit. SPIEN SPIODO ...
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Table 155. SPI Interrupt Status SFR (SPISTAT, Address 0xEA) Bit Mnemonic Default Description 7 BUSY 0 SPI peripheral busy flag. BUSY MMERR 0 SPI multimaster error flag. MMERR SPIRxOF 0 SPI receive overflow error ...
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ADE5166/ADE5169/ADE5566/ADE5569 SS (Slave Select Pin) In SPI slave mode, a transfer is initiated by the assertion of SS low. The SPI port then transmits and receives 8-bit data until the data is concluded by the deassertion of SS according to ...
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SPI INTERRUPT AND STATUS FLAGS The SPI interface has several status flags that indicate the status of the double-buffered receive and transmit registers. Figure 112 shows when the status and interrupt flags are raised. The transmit interrupt occurs when the ...
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ADE5166/ADE5169/ADE5566/ADE5569 2 I C-COMPATIBLE INTERFACE The ADE5166/ADE5169/ADE5566/ADE5569 support a fully 2 2 licensed I C interface. The I C interface is implemented as a full hardware master. SDATA (P0.4/MOSI/SDATA) is the data I/O pin, and SCLK (P0.6/SCLK/T0) is the serial ...
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Table 159 Interrupt Status SFR (SPI2CSTAT, Address 0xEA) Bit Mnemonic Default 7 I2CBUSY 0 6 I2CNOACK 0 5 I2CRxIRQ 0 4 I2CTxIRQ 0 [3:2] I2CFIFOSTAT 00 1 I2CACC_ERR 0 0 I2CTxWR_ERR 0 READ AND WRITE OPERATIONS 1 ...
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ADE5166/ADE5169/ADE5566/ADE5569 RECEIVE AND TRANSMIT FIFOS 2 The I C peripheral has a 4-byte receive FIFO and a 4-byte transmit FIFO. The buffers reduce the overhead associated with using 2 the I C peripheral. Figure 116 shows the ...
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I/O PORTS PARALLEL I/O The ADE5166/ADE5169/ADE5566/ADE5569 use three input/ output ports to exchange data with external devices. In addition to performing general-purpose I/O, some ports are capable of driving an LCD or performing alternate functions for the periph- erals available ...
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ADE5166/ADE5169/ADE5566/ADE5569 I/O REGISTERS Table 161. Extended Port Configuration SFR (EPCFG, Address 0x9F) Bit Mnemonic 7 MOD38_FP21 6 MOD38_FP22 5 MOD38_TxD2 4 MOD38_TxD 3 MOD38_CF1 2 MOD38_SSb 1 MOD38_MISO 0 MOD38_CF2 Table 162. Port 0 Weak Pull-Up Enable SFR (PINMAP0, Address ...
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Table 165. Port 0 SFR (P0, Address 0x80) Bit Bit Address Mnemonic 7 0x87 T1 6 0x86 T0 5 0x85 ZX 4 0x84 3 0x83 CF2 2 0x82 CF1 1 0x81 0 0x80 INT1 1 When an alternate function is ...
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ADE5166/ADE5169/ADE5566/ADE5569 Table 168. Port 0 Alternate Functions Pin No. Alternate Function P0.0 BCTRL external battery control input INT1 external interrupt INT1 wake-up from PSM2 operating mode P0.1 FP19 LCD segment pin P0.2 CF1 ADE calibration frequency output P0.3 CF2 ADE ...
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PORT 0 Port 0 is controlled directly through the bit-addressable Port 0 SFR (P0, Address 0x80). The weak internal pull-ups for Port 0 are configured through the Port 0 weak pull-up enable SFR (PINMAP0, Address 0xB2); they are enabled by ...
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ADE5166/ADE5169/ADE5566/ADE5569 DETERMINING THE VERSION OF THE ADE5166/ADE5169/ADE5566/ADE5569 Each ADE5166/ADE5169/ADE5566/ADE5569 holds in its internal flash registers a value that defines its version. This value helps to determine if users have the latest version of the part. The version of the ADE5166/ADE5169/ADE5566/ADE5569 ...
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... SEATING PLANE VIEW A ROTATED 90° CCW ORDERING GUIDE 1, 2 Model Antitamper ADE5166ASTZF62 Yes ADE5166ASTZF62-RL Yes ADE5169ASTZF62 Yes ADE5169ASTZF62-RL Yes ADE5566ASTZF62 No ADE5566ASTZF62-RL No ADE5569ASTZF62 No ADE5569ASTZF62-RL No ADE8052Z-PRG1 ADE8052Z-DWDL1 ADE8052Z-EMUL1 1 All models have rms LCD, and RTC RoHS Compliant Part. ADE5166/ADE5169/ADE5566/ADE5569 0.75 0.60 1.60 MAX ...
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ADE5166/ADE5169/ADE5566/ADE5569 NOTES Rev Page 154 of 156 ...
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NOTES ADE5166/ADE5169/ADE5566/ADE5569 Rev Page 155 of 156 ...
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ADE5166/ADE5169/ADE5566/ADE5569 NOTES refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). ©2008–2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07411-0-6/10(C) Rev ...