ADE7518ASTZF8-RL Analog Devices Inc, ADE7518ASTZF8-RL Datasheet
ADE7518ASTZF8-RL
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ADE7518ASTZF8-RL Summary of contents
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GENERAL FEATURES Wide supply voltage operation: 2 3.7 V Internal bipolar switch between regulated and battery inputs Ultralow power operation with power saving modes Full operation 1.6 mA (PLL clock dependent) Battery mode: 3.2 mA ...
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ADE7518 TABLE OF CONTENTS General Features ............................................................................... 1 Energy Measurement Features ........................................................ 1 Microprocessor Features .................................................................. 1 Revision History ............................................................................... 3 General Description ......................................................................... 4 Functional Block Diagram .............................................................. 4 Specifications ..................................................................................... 5 Energy Metering ........................................................................... 5 Analog Peripherals ....................................................................... ...
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Flash Memory .................................................................................. 87 Overview ...................................................................................... 87 Flash Memory Organization ...................................................... 88 Using the Flash Memory ............................................................ 88 Protecting the Flash Memory .................................................... 91 In-Circuit Programming ............................................................ 92 Timers ............................................................................................... 93 Timer Registers ............................................................................ 93 Timer 0 and Timer 1 ...
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ADE7518 GENERAL DESCRIPTION 1 The ADE7518 integrates the Analog Devices, Inc., energy (ADE) metering IC analog front end and fixed function DSP solution with an enhanced 8052 MCU core, an RTC, an LCD driver, and all the peripherals to make ...
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SPECIFICATIONS V = 3.3 V ± 5%, AGND = DGND = 0 V, on-chip reference XTAL = 32.768 kHz ENERGY METERING Table 1. Parameter 1 MEASUREMENT ACCURACY Phase Error Between Channels PF = 0.8 Capacitive PF = 0.5 ...
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ADE7518 ANALOG PERIPHERALS Table 2. Parameter POWER-ON RESET (POR) V POR DD Detection Threshold POR Active Timeout Period V POR SWOUT Detection Threshold POR Active Timeout Period V POR INTD Detection Threshold POR Active Timeout Period V POR INTA Detection ...
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DIGITAL INTERFACE Table 3. Parameter LOGIC INPUTS All Inputs Except XTAL1, XTAL2, BCTRL, INT0, INT1, RESET Input High Voltage, V INH Input Low Voltage, V INL BCTRL, INT0, INT1, RESET Input High Voltage, V INH Input Low Voltage, V INL ...
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ADE7518 Parameter POWER SUPPLY CURRENTS Current in Normal Mode (PSM0) Current in PSM1 Current in PSM2 POWER SUPPLY CURRENTS Current in Normal Mode (PSM0) 1 Endurance is qualified as per JEDEC Standard 22 Method A117 and measured at −40°C, +25°C, ...
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TIMING SPECIFICATIONS AC inputs during testing were driven at V and 0.45 V for Logic 0. Timing measurements were made at V minimum for Logic 1 and V maximum for Logic 0, as shown in IL Figure 2. V – ...
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ADE7518 Table 6. SPI Master Mode Timing (SPICPHA = 1) Parameters Parameter Description t SCLK low pulse width SL t SCLK high pulse width SH t Data output valid after SCLK edge DAV t Data input setup time before SCLK ...
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Table 7. SPI Master Mode Timing (SPICPHA = 0) Parameters Parameter Description t SCLK low pulse width SL t SCLK high pulse width SH t Data output valid after SCLK edge DAV t Data output setup before SCLK edge DOSU ...
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ADE7518 Table 8. SPI Slave Mode Timing (SPICPHA = 1) Parameters Parameter Description SCLK edge SS t SCLK low pulse width SL t SCLK high pulse width SH t Data output valid after SCLK edge DAV t ...
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Table 9. SPI Slave Mode Timing (SPICPHA = 0) Parameters Parameter Description SCLK edge SS t SCLK low pulse width SL t SCLK high pulse width SH t Data output valid after SCLK edge DAV t Data ...
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ADE7518 ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. A Table 10. Parameter V to DGND DGND BAT V to DGND DCIN Input LCD Voltage to AGND, LCDVA, 1 LCDVB, LCDVC Analog Input Voltage to AGND, ...
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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS COM3/FP27 COM2/FP28 COM1 COM0 P1.2/FP25 P1.3/T2EX/FP24 P1.4/T2/FP23 P1.5/FP22 P1.6/FP21 P1.7/FP20 P0.1/FP19 P2.0/FP18 P2.1/FP17 P2.2/FP16 LCDVC LCDVP2 Table 12. Pin Function Descriptions Pin No. Mnemonic Description 1 COM3/FP27 Common Output 3 or LCD Segment Output 27. ...
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ADE7518 Pin No. Mnemonic Description 37 P1.0/RxD General-Purpose Digital I/O Port 1.0 or Receiver Data Input (Asynchronous). 38 P0.7/SS/T1 General-Purpose Digital I/O Port 0.7, Slave Select When SPI is in Slave Mode, or Timer 1 Input. 39 P0.6/SCLK/T0 General-Purpose Digital ...
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TYPICAL PERFORMANCE CHARACTERISTICS 2.0 MID CLASS C GAIN = 1 INTERNAL REFERENCE 1.5 1.0 0.5 +25° +85° –40° –0.5 –1.0 –1.5 MID CLASS C –2.0 0.1 1 CURRENT CHANNEL (% ...
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ADE7518 0.5 GAIN = 1 INTERNAL REFERENCE 0.4 0.3 0 3.3V rms I ; 3.3V rms 0 3.43V rms 0 –0 3.13V rms –0.2 –0.3 –0.4 –0.5 0.1 1 CURRENT CHANNEL (% of Full ...
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MID CLASS C GAIN = 16 INTERNAL REFERENCE 1.5 1.0 0.5 +25° –40° –0.5 +85° –1.0 –1.5 MID CLASS C –2.0 0.1 1 CURRENT CHANNEL (% of Full Scale) ...
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ADE7518 TERMINOLOGY Measurement Error The error associated with the energy measurement made by the ADE7518 is defined by the following formula: Percentage Error = ⎛ ⎞ − Energy Register True Energy ⎜ ⎟ × ⎜ ⎟ True Energy ⎝ ⎠ ...
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SFR MAPPING Table 13. Mnemonic Address INTPR 0xFF SCRATCH4 0xFE SCRATCH3 0xFD SCRATCH2 0xFC SCRATCH1 0xFB IPSMF 0xF8 TEMPCAL 0xF7 RTCCOMP 0xF6 BATPR 0xF5 PERIPH 0xF4 B 0xF0 LCDSEGE2 0xED IPSME 0xEC SPISTAT 0xEA SPI2CSTAT 0xEA SPIMOD2 0xE9 I2CADR 0xE9 ...
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ADE7518 POWER MANAGEMENT The ADE7518 has elaborate power management circuitry that manages the regular power supply to battery switchover and power supply failures. The power management functionalities can be accessed directly through the 8052 SFRs (see Table 14). Table 14. ...
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Table 16. Power Management Interrupt Flag SFR (IPSMF, 0xF8) Bit Address Mnemonic Default 7 0xFF FPSR 0 6 0xFE FPSM 0 5 0xFD FSAG 0 4 0xFC Reserved 0 3 0xFB Reserved 0 2 0xFA Reserved 0 1 0xF9 FBSO ...
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ADE7518 Table 21. Scratch Pad 2 SFR (SCRATCH2, 0xFC) Bit Mnemonic Default Description SCRATCH2 0 Value can be written/read in this register. This value is maintained in all the power saving modes. Table 22. Scratch Pad 3 ...
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POWER SUPPLY ARCHITECTURE The ADE7518 has two power supply inputs, V requires only a single 3.3 V power supply battery backup, or secondary power supply, with a maximum of 3.7 V, can be connected to the V ...
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ADE7518 POWER SUPPLY MANAGEMENT (PSM) INTERRUPT The power supply management (PSM) interrupt alerts the 8052 core of power supply events. The PSM interrupt is disabled by default. Setting the EPSM bit in the Interrupt Enable and Priority 2 SFR (IEIP2, ...
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Battery Switchover and Power Supply Restored PSM Interrupt The ADE7518 can be configured to generate a PSM interrupt when the source of V changes from V SWOUT battery switchover. Setting the EBSO bit in the Power Management Interrupt Enable SFR ...
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ADE7518 USING THE POWER SUPPLY FEATURES In an energy meter application, the 3.3 V power supply (V is typically generated from the ac line voltage and regulated to 3 voltage regulator IC. The preregulated dc voltage, typically ...
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Table 25. Power Supply Event Timing Operating Modes Parameter Time Description min Time between when min Time between when typ Time between when V 3 battery switchover. ...
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ADE7518 OPERATING MODES PSM0 (NORMAL MODE) In PSM0, normal operating mode, V SWOUT All of the analog circuitry and digital circuitry powered by V and V are enabled by default. In normal mode, the INTD INTA default clock frequency, f ...
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V PERIPHERALS AND WAKE-UP EVENTS Some of the 3.3 V peripherals are capable of waking the ADE7518 from PSM2. The events that can cause the ADE7518 to wake up from PSM2 are listed in the Wake-Up Event column in ...
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ADE7518 TRANSITIONING BETWEEN OPERATING MODES The operating mode of the ADE7518 is determined by the power supply connected Therefore, changes in the power SWOUT supply, such as when V switches from V SWOUT V switches to V ...
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ENERGY MEASUREMENT The ADE7518 offers a fixed function, energy measurement, digital processing core that provides all the information needed to measure energy in single-phase energy meters. The part provides two ways to access the energy measurements: direct access through SFRs ...
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ADE7518 Table 29. Energy Measurement SFRs Address R/W Mnemonic 0x91 R/W MADDPT 0x92 R/W MDATL 0x93 R/W MDATM 0x94 R/W MDATH 0xD1 R VRMSL 0xD2 R VRMSM 0xD3 R VRMSH 0xD4 R IRMSL 0xD5 R IRMSM 0xD6 R IRMSH 0xD9 ...
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ENERGY MEASUREMENT REGISTERS Table 30. Energy Measurement Register List Address Length MADDPT[6:0] Mnemonic R/W (Bits) 0x01 WATTHR R 24 0x02 RWATTHR R 24 0x03 LWATTHR R 24 0x04 VARHR R 24 0x05 RVARHR R 24 0x06 LVARHR R 24 0x07 ...
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ADE7518 Address Length MADDPT[6:0] Mnemonic R/W (Bits) 0x29 CF2NUM R/W 16 0x2A CF2DEN R/W 16 0x3B Reserved 0x3C Reserved 0x3D Reserved 0x3E Reserved 0x3F Reserved ENERGY MEASUREMENT INTERNAL REGISTERS DETAILS Table 31. MODE1 Register (0x0B) Bit Mnemonic Default 7 SWRST ...
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Table 33. WAVMODE Register (0x0D) Bit Mnemonic Default WAV2SEL[2:0] 000 WAV1SEL[2:0] 000 DTRT[1:0] 00 Table 34. NLMODE Register (0x0E) Bit Mnemonic Default 7 DISVARCMP 0 6 IRMSNOLOAD ...
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ADE7518 Table 35. ACCMODE Register (0x0F) Bit Mnemonic Default Description Reserved 0 These bits should be left at their default value for proper operation. 5 VARSIGN 0 Configuration bit to select the event that triggers a reactive ...
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Table 38. Interrupt Status 2 SFR (MIRQSTM, 0xDD) Bit Interrupt Flag Description 7 CF2 Logic 1 indicates that a pulse on CF2 has been issued. The flag is set even if the CF2 pulse output is not enabled by clearing ...
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ADE7518 ANALOG INPUTS The ADE7518 has two fully differential voltage input channels. The maximum differential input voltage for input pairs V and ±0 Each analog input channel has a programmable gain amplifier (PGA) with ...
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ANALOG-TO-DIGITAL CONVERSION Each ADE7518 has two Σ-Δ analog-to-digital converters (ADCs). The outputs of these ADCs are mapped directly to waveform sampling SFRs (Address 0xE2 to Address 0xE7) and are used for energy measurement internal digital signal processing. In PSM1 (battery ...
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ADE7518 Antialiasing Filter Figure 38 also shows an analog low-pass filter (RC) on the input to the modulator. This filter is present to prevent aliasing, an artifact of all sampled systems. Aliasing means that frequency components in the input signal ...
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Voltage Channel ADC Figure 41 shows the ADC and signal processing chain for the voltage channel. In waveform sampling mode, the ADC outputs a signed, twos complement, 24-bit data-word at a maximum of 25.6 kSPS (MCLK/160). The ADC produces an ...
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ADE7518 POWER QUALITY MEASUREMENTS Zero-Crossing Detection Each ADE7518 has a zero-crossing detection circuit on the voltage channel. This zero crossing is used to produce a zero- crossing internal signal (ZX) and is used in calibration mode. The zero-crossing is generated ...
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Line Voltage SAG Detection In addition to detection of the loss of the line voltage signal (zero crossing), the ADE7518 can also be programmed to detect when the absolute value of the line voltage drops below a certain peak value ...
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ADE7518 PHASE COMPENSATION The ADE7518 must work with transducers that can have inherent phase errors. For example, a phase error of 0.1° to 0.3° is not uncommon for a current transformer (CT). These phase errors can vary from part to ...
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Current Channel RMS Calculation Each ADE7518 simultaneously calculates the rms values for the current and voltage channels in different registers. Figure 48 shows the detail of the signal processing chain for the rms calculation on the current channel. The current ...
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ADE7518 Voltage Channel RMS Calculation Figure 50 shows details of the signal processing chain for the rms calculation on the voltage channel. The voltage channel rms value is processed from the samples used in the voltage channel waveform sampling mode ...
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FREQUENCY (Hz) Figure 51. Frequency Response of LPF2 Active Power Gain Calibration Figure 52 shows the signal processing chain for the active power calculation in the ADE7518. As explained previously, ...
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ADE7518 ACTIVE ENERGY CALCULATION As stated in the Active Power Calculation section, power is defined as the rate of energy flow. This relationship can be expressed mathematically in Equation 11 where power ...
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Figure 53 shows this energy accumulation for full-scale signals (sinusoidal) on the analog inputs. The three displayed curves illustrate the minimum period of time it takes the energy register to roll over when the active power gain register contents are ...
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ADE7518 ACTIVE ENERGY NO LOAD THRESHOLD ACTIVE POWER NO LOAD THRESHOLD APSIGN FLAG APNOLOAD POS INTERRUPT STATUS REGISTERS Figure 55. Energy Accumulation in Watt-Absolute Accumulation Mode Active Energy Pulse Output All of the ADE7518 circuitry has a pulse output whose ...
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When a new half-line cycle is written in the LINCYC register, the LWATTHR register is reset, and a new accumulation starts at the next zero crossing. The number of half-line cycles is then counted until LINCYC is reached. This implementation ...
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ADE7518 Reactive Power Gain Calibration Figure 58 shows the signal processing chain for the ADE7518 reactive power calculation. As explained in the Reactive Power Calculation section, the reactive power is calculated by applying a low-pass filter to the instantaneous reactive ...
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When SAVARM in the ACCMODE register (0x0F) is set, the reactive power is accumulated depending on the sign of the active power. When active power is positive, the reactive power is added the reactive energy register. ...
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ADE7518 Integration Time Under Steady Load: Reactive Energy As mentioned in the Active Energy Calculation section, the discrete time sample period (T) for the accumulation register is 1.22 μs (5/MCLK). With full-scale sinusoidal signals on the analog inputs and the ...
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VAR Absolute Accumulation Mode The ADE7518 is placed in absolute accumulation mode by setting the ABSVARM bit in the ACCMODE register (0x0F). In absolute accumulation mode, the reactive energy accumulation is done by using the absolute reactive power and ignoring ...
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ADE7518 APPARENT POWER CALCULATION Apparent power is defined as the maximum power that can be delivered to a load. V and I are the effective voltage and rms rms current delivered to the load, respectively. Therefore, the apparent power (AP) ...
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APPARENT ENERGY CALCULATION The apparent energy is given as the integer of the apparent power. = ∫ Apparent Energy Apparent Power The ADE7518 achieves the integration of the apparent power signal by continuously accumulating the apparent power signal in an ...
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ADE7518 Apparent Energy Pulse Output All ADE7518 circuitry has a pulse output whose frequency is proportional to apparent power (see the Energy-to-Frequency Conversion section). This pulse frequency output uses the calibrated signal after VAGAIN. This output can also be used ...
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ENERGY-TO-FREQUENCY CONVERSION The ADE7518 also provides two energy-to-frequency conversions for calibration purposes. After initial calibration at manufacturing, the manufacturer or end customer often verifies the energy meter calibration. One convenient way to do this is for the manufacturer to provide ...
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ADE7518 ENERGY REGISTER SCALING The ADE7518 provides measurements of active, reactive, and apparent energies that use separate paths and filtering for calcula- tion. The difference in data paths may result in small differences in LSB weight between active, reactive, and ...
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MCU CORE ARCHITECTURE The ADE7518 has an 8052 MCU core and uses the 8051 instruc- tion set. Some of the standard 8052 peripherals, such as the UART, have been enhanced. This section describes the standard 8052 core and its ...
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ADE7518 Table 47. Program Control SFR (PCON, 0x87) Bit Default Description 7 0 SMOD Bit. Double baud rate control Reserved. Should be left cleared. Table 48. Data Pointer Low SFR (DPL, 0x82) Bit Default Description 7 ...
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BASIC 8052 REGISTERS Program Counter (PC) The program counter holds the 2-byte address of the next instruc- tion to be fetched. The PC is initialized with 0x00 at reset and is incremented after each instruction is performed. Note that the ...
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ADE7518 STANDARD 8052 SFRS The standard 8052 special function registers include the ACC, B, PSW, DPTR, and SP SFRs described in the Basic 8052 Registers section. The standard 8052 SFRs also define the timers, the serial port interface, the interrupts, ...
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ACCESSIBLE BY ACCESSIBLE BY INDIRECT ADDRESSING DIRECT ADDRESSING ONLY 0x80 0x7F ACCESSIBLE BY DIRECT AND INDIRECT ADDRESSING 0x00 GENERAL-PURPOSE RAM SPECIAL FUNCTION REGISTERS (SFRs) Figure 70. General-Purpose RAM and SFR Memory Address Overlap Both direct and indirect addressing can ...
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ADE7518 Direct Addressing With direct addressing, the value at the source address is moved to the destination address. Direct addressing provides the fastest execution time of all the addressing modes when an instruction is performed between registers. Note that indirect ...
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INSTRUCTION SET Table 54 documents the number of clock cycles required for each instruction. Most instructions are executed in one or two clock cycles, resulting in a 4-MIPS peak performance. Table 54. Instruction Set Mnemonic Description Arithmetic ADD A, Rn ...
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ADE7518 Mnemonic Description RLC A Rotate A left through carry RR A Rotate A right RRC A Rotate A right through carry Data Transfer MOV A, Rn Move register to A MOV A, @Ri Move indirect memory to A MOV ...
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Mnemonic Description JNC rel Jump on carry = 0 JZ rel Jump on accumulator = 0 JNZ rel Jump on accumulator ≠ 0 DJNZ Rn, rel Decrement register, JNZ relative LJMP Long jump unconditional LCALL addr16 Long jump to subroutine ...
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ADE7518 SUBB A, Source This instruction subtracts the source byte and the carry (borrow) flag from the accumulator. It references the carry (borrow) status flag. Affected Status Flags C Set if there is a borrow needed for Bit 7. Cleared ...
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DUAL DATA POINTERS The ADE7518 incorporates two data pointers. The second data pointer is a shadow data pointer and is selected via the Data Pointer Control SFR (DPCON, 0xA7). DPCON features automatic hard- ware postincrement and postdecrement, as well as ...
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ADE7518 INTERRUPT SYSTEM The unique power management architecture of the ADE7518 includes an operating mode (PSM2) where the 8052 MCU core is shut down. Events can be configured to wake the 8052 MCU core from the PSM2 operating mode. A ...
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Table 59. Interrupt Priority SFR (IP, 0xB8) Bit Address Mnemonic 7 0xBF PADE 6 0xBE Reserved 5 0xBD PT2 4 0xBC PS 3 0xBB PT1 2 0xBA PX1 1 0xB9 PT0 0 0xB8 PX0 Table 60. Interrupt Enable and Priority ...
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ADE7518 INTERRUPT FLAGS The interrupt flags and status flags associated with the interrupt vectors are shown in Table 62 and Table 63. Most of the interrupts have flags associated with them. Table 62. Interrupt Flags Interrupt Source Flag IE0 TCON.1 ...
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IPSMF FPSM PSM (IPSMF.6) IPSME MIDNIGHT RTC ALARM MIRQSTH MIRQSTM MIRQSTL ADE MIRQENH MIRQENM MIRQENL WATCHDOG TIMEOUT WATCHDOG WDIR IT0 0 INT0 EXTERNAL INTERRUPT 0 1 IT0 TF0 TIMER 0 IT1 0 EXTERNAL INT1 INTERRUPT 1 1 IT1 TF1 TIMER ...
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ADE7518 INTERRUPT VECTORS When an interrupt occurs, the program counter is pushed onto the stack, and the corresponding interrupt vector address is loaded into the program counter. When the interrupt service routine is complete, the program counter is popped off ...
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WATCHDOG TIMER The watchdog timer generates a device reset or interrupt within a reasonable amount of time if the ADE7518 enters an erroneous state, possibly due to a programming error or electrical noise. The watchdog is enabled by default with ...
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ADE7518 Table 66. Watchdog and Flash Protection Byte in Flash (Flash Address = 0x3FFA) Bit Mnemonic Default 7 WDPROT_PROTKY7 PROTKY[6:0] 0xFF Writing to the Watchdog Timer SFR (WDCON, 0xC0) Writing data to the WDCON SFR involves ...
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LCD DRIVER Using shared pins, the LCD module is capable of directly driving an LCD panel of 17 × 4 segments without compromising any ADE7518 functions capable of driving LCDs with 2×, 3×, and 4× multiplexing. The LCD ...
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ADE7518 Table 69. LCD Configuration X SFR (LCDCONX, 0x9C) Bit Mnemonic Default 7 Reserved 0 6 EXTRES Reserved 0 Table 70. LCD Configuration Y SFR (LCDCONY, 0xB1) Bit Mnemonic Default 7 Reserved 0 6 INV_LVL 0 ...
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Table 72. LCD Frame Rate Selection for f FD3 FD2 FD1 FD0 f (Hz) LCD 256 170 128 102 85.3 ...
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ADE7518 Table 75. LCD Pointer SFR (LCDPTR, 0xAC) Bit Mnemonic Default 7 0 R/W 6 Reserved ADDRESS 0 Table 76. LCD Data SFR (LCDDAT, 0xAE) Bit Mnemonic Default LCDDATA 0 Table 77. LCD ...
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BLINK MODE Blink mode is enabled by setting the BLINKEN bit in the LCD Configuration SFR (LCDCON, 0x95). This mode is used to alternate between the LCD on state and LCD off state so that the LCD screen appears to ...
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ADE7518 LCD EXTERNAL CIRCUITRY The voltage generation selection is made by setting Bit EXTRES in the LCD Configuration X SFR (LCDCONX, 0x9C). This bit is cleared by default and needs to be set to enable an external resistor ladder. External ...
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FLASH MEMORY OVERVIEW Flash memory is a type of nonvolatile memory that is in-circuit programmable. The default state of a byte of flash memory is 0xFF (erased). When a byte of flash memory is programmed, the required bits change from ...
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ADE7518 FLASH MEMORY ORGANIZATION The flash memory provided by the ADE7518 are seg- mented into 32 pages of 512 bytes each the user to decide which flash memory to allocate for data memory. ...
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ECON—Flash/EE Memory Control SFR Programming flash memory is done through the Flash Control SFR (ECON, 0xB9). This SFR allows the user to read, write, erase, or verify the flash memory method of security, a key ...
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ADE7518 Table 87. Flash Read Protection SFR (PROTR, 0xBF) Bit Mnemonic Default Description PROTR 0xFF This SFR is used to write the read protection bits for Page 0 to Page 31 of the flash memory (see the ...
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PROTECTING THE FLASH MEMORY Two forms of protection are offered for this flash memory: read protection and write/erase protection. The read protection ensures that any pages that are read protected are not able to be read by the end user. ...
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ADE7518 Enabling Flash Protection by Emulator Commands Another way to set the flash protection bytes is to use some reserved emulator commands available only in download mode. These commands write directly to the SFRs and can be used to duplicate ...
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TIMERS The ADE7518 has three 16-bit timer/counters: Timer/Counter 0, Timer/Counter 1, and Timer/Counter 2. The timer/counter hardware is included on chip to relieve the processor core of overhead inherent in implementing timer/counter functionality in software. Each timer/counter consists of two ...
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ADE7518 Table 93. Timer/Counter 0 and Timer/Counter 1 Control SFR (TCON, 0x88) Bit Address Mnemonic Default 7 0x8F TF1 0 6 0x8E TR1 0 5 0x8D TF0 0 4 0x8C TR0 0x8B IE1 0x8A ...
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Table 95. Timer 0 High Byte SFR (TH0, 0x8C) Bit Mnemonic Default Description TH0 0 Timer 0 Data High Byte. Table 96. Timer 0 Low Byte SFR (TL0, 0x8A) Bit Mnemonic Default Description TL0 ...
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ADE7518 Mode 2 (8-Bit Timer/Counter with Autoreload) Mode 2 configures the timer register as an 8-bit counter (TL0) with automatic reload, as shown in Figure 84. Overflow from TL0 not only sets TF0 but also reloads TL0 with the contents ...
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CORE P1.4/T2 CONTROL TR2 RELOAD TRANSITION DETECTOR P1.3/ T2EX CONTROL EXEN2 Figure 86. Timer/Counter 2, 16-Bit Autoreload Mode f CORE P1.4/T2 CONTROL TR2 ...
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ADE7518 PLL The ADE7518 is intended for use with a 32.768 kHz watch crystal. A PLL locks onto a multiple of this frequency to provide a stable 4.096 MHz clock for the system. The core can operate at this frequency ...
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Table 106. Peripheral Configuration SFR (PERIPH, 0xF4) Bit Mnemonic Default 7 RXFLAG 0 6 VSWSOURCE 1 5 VDD_OK 1 4 PLL_FLT 0 3 REF_BAT_EN 0 2 Reserved RXPROG[1:0] 00 Table 107. Start ADC Measurement SFR (ADCGO, ...
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ADE7518 REAL-TIME CLOCK The ADE7518 has an embedded real-time clock (RTC), as shown in Figure 88. The external 32.768 kHz crystal is used as the clock source for the RTC. Calibration is provided to compensate the nominal crystal frequency and ...
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Table 109. RTC Configuration SFR (TIMECON, 0xA1) Bit Mnemonic Default Description 7 MIDNIGHT 0 Midnight Flag. This bit is set when the RTC rolls over to 00:00:00:00. It can be cleared by the user to indicate that the midnight event ...
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ADE7518 Table 114. Alarm Interval SFR (INTVAL, 0xA6) Bit Mnemonic Default Description INTVAL 0 The interval timer counts according to the time base established in the ITS[1:0] bits of the RTC Configuration SFR (TIMECON, 0xA1). Once the ...
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READ AND WRITE OPERATIONS Writing to the RTC Registers The RTC circuitry runs off a 32.768 kHz clock. The timekeeping registers, Hundredths of a Second Counter SFR (HTHSEC, 0xA2), Seconds Counter SFR (SEC, 0xA3), Minutes Counter SFR (MIN, 0xA4), and ...
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ADE7518 Take care when changing the interval timer time base. The recommended procedure is as follows the Alarm Interval SFR (INTVAL, 0xA6) is going to be modified, write to this register first. Then, wait for one 128 Hz ...
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UART SERIAL INTERFACE The ADE7518 UART can be configured in one of four modes. • Shift register with baud rate fixed at f • 8-bit UART with variable baud rate • 9-bit UART with baud rate fixed at f • ...
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ADE7518 Table 122. Serial Port Buffer SFR (SBUF, 0x99) Bit Mnemonic Default SBUF 0 Table 123. Enhanced Serial Baud Rate Control SFR (SBAUDT, 0x9E) Bit Mnemonic Default 7 OWE ...
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Table 125. Common Baud Rates Using UART Timer with a 4.096 MHz PLL Clock Ideal Baud CD 115,200 0 115,200 1 57,600 0 57,600 1 38,400 0 38,400 1 38,400 2 19,200 0 19,200 1 19,200 2 19,200 3 9600 ...
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ADE7518 UART OPERATION MODES Mode 0 (Shift Register with Baud Rate Fixed at f Mode 0 is selected when the SM0 and SM1 bits in the Serial Communications Control Register Bit Description SFR (SCON, 0x98) are cleared. In this shift ...
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To transmit, the eight data bits must be written into the Serial Port Buffer SFR (SBUF, 0x99). The ninth bit must be written to TB8 in the Serial Communications Control Register SFR (SCON, 0x98). When transmission is initiated, the eight ...
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ADE7518 TCLK puts Timer 2 into its baud rate generator mode, as shown in Figure 92. In this case, the baud rate is given by the following formula: Mode 1 or Mode 3 Baud Rate = f CORE ( [ ...
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SBAUDF is the fractional divider ratio required to achieve the required baud rate. The appropriate value for SBAUDF can be calculated with the following formula: ⎛ f ⎜ = × CORE SBAUDF 64 ⎜ + × DIV SBTH × 16 ...
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ADE7518 SERIAL PERIPHERAL INTERFACE (SPI) The ADE7518 integrates a complete hardware serial peripheral interface on-chip. The SPI is full duplex so that eight bits of data are synchronously transmitted and simultaneously received. This SPI implementation is double buffered, allowing users ...
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Table 129. SPI Configuration SFR 1 (SPIMOD1, 0xE8) Bit Address Mnemonic 0xEF to 0xEE Reserved 0 5 0xED INTMOD 0 4 0xEC AUTO_SS 1 3 0xEB SS_EN 0 2 0xEA RxOFW 0xE9 to0xE8 ...
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ADE7518 Table 130. SPI Configuration SFR 2 (SPIMOD2, 0xE9) Bit Mnemonic Default Description 7 SPICONT 0 Master Mode, SPI Continuous Transfer Mode Enable Bit. SPICONT SPIEN 0 SPI Interface Enable Bit. SPIEN SPIODO 0 ...
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Table 131. SPI Interrupt Status SFR (SPISTAT, 0xEA) Bit Mnemonic Default Description 7 BUSY 0 SPI Peripheral Busy Flag. BUSY MMERR 0 SPI Multimaster Error Flag. MMERR SPIRxOF 0 SPI Receive Overflow Error Flag. ...
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ADE7518 SS (Slave Select Pin) In SPI slave mode, a transfer is initiated by the assertion of SS low. The SPI port then transmits and receives 8-bit data until the data is concluded by the deassertion of SS according to ...
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SPI INTERRUPT AND STATUS FLAGS The SPI interface has several status flags that indicate the status of the double-buffered receive and transmit registers. Figure 96 shows when the status and interrupt flags are raised. The transmit interrupt occurs when the ...
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ADE7518 2 I C-COMPATIBLE INTERFACE The ADE7518 supports a fully licensed I interface is implemented as a full hardware master. SDATA is the data I/O pin, and SCLK is the serial clock. These two pins are shared with the MOSI ...
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Table 135 Interrupt Status Register SFR (SPI2CSTAT, 0xEA) Bit Mnemonic Default 7 I2CBUSY 0 6 I2CNOACK 0 5 I2CRxIRQ 0 4 I2CTxIRQ I2CFIFOSTAT[1: I2CACC_ERR 0 0 I2CTxWR_ERR 0 READ AND WRITE ...
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ADE7518 RECEIVE AND TRANSMIT FIFOS 2 The I C peripheral has a 4-byte receive FIFO and a 4-byte transmit FIFO. The buffers reduce the overhead associated with using 2 the I C peripheral. Figure 100 shows the ...
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I/O PORTS PARALLEL I/O The ADE7518 uses three input/output ports to exchange data with external devices. In addition to performing general-purpose I/O, some are capable of driving an LCD or performing alternate functions for the peripherals available on-chip. In general, ...
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ADE7518 I/O REGISTERS Table 137. Extended Port Configuration SFR (EPCFG, 0x9F) Bit Mnemonic 7 MOD38_FP21 6 MOD38_FP22 5 MOD38_FP23 4 MOD38_TxD 3 MOD38_CF1 2 MOD38_SSb 1 MOD38_MISO 0 MOD38_CF2 Table 138. Port 0 Weak Pull-Up Enable SFR (PINMAP0, 0xB2) Bit ...
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Table 141. Port 0 SFR (P0, 0x80) Bit Address Mnemonic 7 0x87 T1 6 0x86 T0 5 0x85 4 0x84 3 0x83 CF2 2 0x82 CF1 1 0x81 0 0x80 INT1 1 When an alternate function is chosen for a ...
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ADE7518 Table 144. Port 0 Alternate Functions Pin No. Alternate Function P0.0 BCTRL External Battery Control Input INT1 External Interrupt INT1 Wake-up from PSM2 Operating Mode P0.1 FP19 LCD Segment Pin P0.2 CF1 ADE Calibration Frequency Output P0.3 CF2 ADE ...
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PORT 0 Port 0 is controlled directly through the bit-addressable Port 0 SFR (P0, 0x80). The weak internal pull-ups for Port 0 are confi- gured through the Port 0 Weak Pull-Up Enable SFR (PINMAP0, 0xB2); they are enabled by default. ...
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ADE7518 DETERMINING THE VERSION OF THE ADE7518 The ADE7518 holds in its internal flash registers a value that defines its version. This value helps to determine if users have the latest version of the part. The ADE7518 version corresponding to ...
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... OUTLINE DIMENSIONS 1.45 1.40 1.35 SEATING PLANE VIEW A ROTATED 90° CCW ORDERING GUIDE Model Antitamper 1 ADE7518ASTZF8 No 1 ADE7518ASTZF8- ADE7518ASTZF16 No 1 ADE7518ASTZF16- RoHS Compliant Part. 0.75 0.60 1.60 MAX 0. PIN 1 0.20 0.09 7° 3.5° 16 0° 17 0.08 VIEW A COPLANARITY 0.50 BSC ...
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ADE7518 NOTES 2 Purchase of licensed I C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I 2 Rights to use these components system, ...