ADE7566ASTZF16-RL Analog Devices Inc, ADE7566ASTZF16-RL Datasheet - Page 65
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ADE7566ASTZF16-RL
Manufacturer Part Number
ADE7566ASTZF16-RL
Description
IC,Power Metering,QFP,64PIN,PLASTIC
Manufacturer
Analog Devices Inc
Specifications of ADE7566ASTZF16-RL
Applications
Energy Measurement
Core Processor
8052
Program Memory Type
FLASH (16 kB)
Controller Series
ADE75xx
Ram Size
512 x 8
Interface
I²C, SPI, UART
Number Of I /o
20
Voltage - Supply
3.135 V ~ 3.465 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
64-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ADE7566ASTZF16-RL
Manufacturer:
Analog Devices Inc
Quantity:
10 000
Figure 67 shows this energy accumulation for full-scale signals
(sinusoidal) on the analog inputs. The three displayed curves
illustrate the minimum period of time it takes the energy register
to roll over when the active power gain register contents are
0x7FF, 0x000, and 0x800. The watt gain register is used to carry
out power calibration in the ADE7116/ADE7156/ADE7166/
ADE7169/ADE7566/ADE7569. As shown, the fastest
integration time occurs when the watt gain register is set to
maximum full scale, that is, 0x7FF.
0x7F,FFFF
0x3F,FFFF
Note that the energy register contents roll over to full-scale
negative (0x800000) and continue to increase in value when the
power or energy flow is positive (see Figure 67). Conversely, if
the power is negative, the energy register underflows to full-
scale positive (0x7FFFFF) and continues to decrease in value.
Using the interrupt enable register (MIRQENM, Address 0xDA),
the ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/
ADE7569 can be configured to issue an ADE interrupt to the
8052 core when the active energy register is half full (positive
or negative) or when an overflow or underflow occurs.
Integration Time Under Steady Load: Active Energy
As mentioned in the Active Energy Calculation section, the
discrete time sample period (T) for the accumulation register is
1.22 μs (5/MCLK). With full-scale sinusoidal signals on the
analog inputs and the WGAIN register (Address 0x1D) set to
0x000, the average word value from each LPF2 is 0xCCCCD
(see Figure 64). The maximum positive value that can be stored
in the internal 49-bit register is 2
before it overflows. The integration time under these conditions
when WDIV = 0 is calculated in the following equation:
0x00,0000
0x40,0000
0x80,0000
WATTHR[23:0]
Time =
0
Figure 67. Energy Register Rollover Time for Full-Scale Power
xFFFF,
0
xCCCCD
3.41
FFFF,
(Minimum and Maximum Power Gain)
6.82
FFFF
10.2
×
. 1
22
μ
48
s
13.7
(or 0xFFFF,FFFF,FFFF)
=
409
6 .
sec
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
TIME (Minutes)
=
. 6
WGAIN = 0x7FF
WGAIN = 0x000
WGAIN = 0x800
82
min
(16)
Rev. B | Page 65 of 152
When WDIV is set to a value other than 0, the integration time
varies, as shown in Equation 17.
Active Energy Accumulation Modes
Watt-Signed Accumulation Mode
The ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/
ADE7569 active energy default accumulation mode is a watt-
signed accumulation based on the active power information.
Watt Positive-Only Accumulation Mode
The ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/
ADE7569 are placed in watt positive-only accumulation mode
by setting the POAM bit (Bit 1) in the ACCMODE register
(Address 0x0F). In this mode, the energy accumulation is done
only for positive power, ignoring any occurrence of negative
power above or below the no load threshold (see Figure 68).
The CF pulse also reflects this accumulation method when in
this mode. The default setting for this mode is off. Detection of
the transitions in the direction of power flow and detection of
no load threshold are active in this mode.
Watt-Absolute Accumulation Mode
The ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/
ADE7569 are placed in watt-absolute accumulation mode by
setting the ABSAM bit (Bit 0) in the ACCMODE register
(Address 0x0F). In this mode, the energy accumulation is done
using the absolute active power, ignoring any occurrence of
power below the no load threshold (see Figure 69). The CF
pulse also reflects this accumulation method when in this
mode. The default setting for this mode is off. Detection of the
transitions in the direction of power flow, and detection of no
load threshold are active in this mode.
Figure 68. Energy Accumulation in Positive-Only Accumulation Mode
ACTIVE ENERGY
Time = Time
ACTIVE POWER
APSIGN FLAG
THRESHOLD
THRESHOLD
NO-LOAD
NO-LOAD
WDIV = 0
INTERRUPT STATUS REGISTERS
× WDIV
POS
NEG
POS
(17)