ADF4110BRUZ-RL Analog Devices Inc, ADF4110BRUZ-RL Datasheet - Page 12

• Manufacturer Part Number: ADF4110BRUZ-RL
• Description: SINGLE PLL, 0.55GHz
• Manufacturer: Analog Devices Inc
• Type: Clock/Frequency Synthesizer (RF)r

Specifications of ADF4110BRUZ-RL

• Pll: Yes
• Input: Clock
• Output: Clock
• Number Of Circuits: 1
• Ratio - Input:output: 2:1
• Differential - Input:output: Yes/No
• Frequency - Max: 550MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP
• Frequency-max: 550MHz
• Number Of Elements: 1
• Supply Current: 5.5mA
• Pll Input Freq (min): 5MHz
• Pll Input Freq (max): 550MHz
• Operating Supply Voltage (typ): 3/5V
• Operating Temp Range: -40C to 85C
• Package Type: TSSOP
• Output Frequency Range: Up to 200MHz
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 5.5V
• Operating Temperature Classification: Industrial
• Pin Count: 16
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-ADF411XEBZ1 - BOARD EVAL FOR ADF411X NO CHIP
• Lead Free Status / Rohs Status: Compliant

ADF4110/ADF4111/ADF4112/ADF4113
CIRCUIT DESCRIPTION
REFERENCE INPUT SECTION
The reference input stage is shown in Figure 28. SW1 and SW2
are normally closed switches. SW3 is normally open. When
power-down is initiated, SW3 is closed and SW1 and SW2 are
opened. This ensures that there is no loading of the REF
on power-down.
RF INPUT STAGE
The RF input stage is shown in Figure 29. It is followed by a
two-stage limiting amplifier to generate the current mode logic
(CML) clock levels needed for the prescaler.
PRESCALER (P/P + 1)
Along with the A and B counters, the dual-modulus prescaler
(P/P + 1) enables the large division ratio, N, to be realized (N =
BP + A). The dual-modulus prescaler, operating at CML levels,
takes the clock from the RF input stage and divides it down to a
manageable frequency for the CMOS A and B counters. The
prescaler is programmable; it can be set in software to 8/9,
16/17, 32/33, or 64/65. It is based on a synchronous 4/5 core.
RF
RF
REF
IN
IN
A
B
IN
GENERATOR
NC
POWER-DOWN
BIAS
Figure 28. Reference Input Stage
SW1
CONTROL
Figure 29. RF Input Stage
NO
500Ω
NC
SW3
SW2
1.6V
100kΩ
500Ω
BUFFER
AGND
AV
DD
TO R COUNTER
IN
pin
Rev. C | Page 12 of 28
A AND B COUNTERS
The A and B CMOS counters combine with the dual-modulus
prescaler to allow a wide ranging division ratio in the PLL
feedback counter. The counters are specified to work when the
prescaler output is 200 MHz or less. Thus, with an RF input
frequency of 2.5 GHz, a prescaler value of 16/17 is valid but a
value of 8/9 is not.
Pulse Swallow Function
The A and B counters, in conjunction with the dual-modulus
prescaler, make it possible to generate output frequencies that
are spaced only by the reference frequency divided by R. The
equation for the VCO frequency is
where:
f
(VCO)
P = preset modulus of dual-modulus prescaler
B = preset divide ratio of binary 13-bit counter(3 to 8191)
A = preset divide ratio of binary 6-bit swallow counter (0 to 63)
f
oscillator
R = preset divide ratio of binary 14-bit programmable reference
counter (1 to 16383)
R COUNTER
The 14-bit R counter allows the input reference frequency to be
divided down to produce the reference clock to the phase
frequency detector (PFD). Division ratios from 1 to 16,383 are
allowed.
VCO
REFIN
INPUT STAGE
= output frequency of external voltage controlled oscillator
= output frequency of the external reference frequency
FROM RF
MODULUS
CONTROL
N = BP + A
f
VCO
PRESCALER
Figure 30. A and B Counters
P/P + 1
= [(P × B) + A]f
LOAD
LOAD
COUNTER
COUNTER
13-BIT B
REFIN
6-BIT A
/R
TO PFD