ADF4156BRUZ-RL Analog Devices Inc, ADF4156BRUZ-RL Datasheet - Page 20

• Manufacturer Part Number: ADF4156BRUZ-RL
• Description: IC,FREQUENCY SYNTHESIZER,CMOS,TSSOP,16PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Type: Fractional N Synthesizer (RF)r

Specifications of ADF4156BRUZ-RL

• Design Resources: Low-Noise Microwave fractional-N PLL using active loop filter and RF prescaler (CN0174)
• Pll: Yes
• Input: CMOS
• Output: Clock
• Number Of Circuits: 1
• Ratio - Input:output: 2:1
• Differential - Input:output: Yes/No
• Frequency - Max: 6GHz
• Divider/multiplier: Yes/Yes
• Voltage - Supply: 2.7 V ~ 3.3 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP
• Frequency-max: 6GHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADF4156
PHASE RESYNC
The output of a fractional-N PLL can settle to any MOD phase
offset with respect to the input reference, where MOD is the
fractional modulus. The phase resync feature in the ADF4156 is
used to produce a consistent output phase offset with respect to
the input reference. This is necessary in applications where the
output phase and frequency are important, such as digital beam
forming. See the Phase Programmability section for information
about how to program a specific RF output phase when using
the phase resync feature.
Phase resync is enabled by setting Bits DB[20:19] in Register R4
to 10. When phase resync is enabled, an internal timer generates
sync signals at intervals of t
formula:
where:
t
CLK_DIV_VALUE is the decimal value programmed in
Bit DB[18:7] of Register R4. This value can be any integer in the
range of 1 to 4095.
MOD is the modulus value programmed in Bit DB[14:3] of
Register R2.
When a new frequency is programmed, the second sync pulse
after the LE rising edge is used to resynchronize the output
phase to the reference. The t
a value that is at least as long as the worst-case lock time. Doing
so guarantees that the phase resync occurs after the last cycle
slip in the PLL settling transient.
In the example shown in Figure 24, the PFD reference is
25 MHz and the MOD value is 125 for a 200 kHz channel
spacing. Therefore, t
CLK_DIV_VALUE to 80.
PFD
is the PFD reference period.
t
SYNC
= CLK_DIV_VALUE × MOD × t
SYNC
is set to 400 μs by programming
SYNC
SYNC
as indicated by the following
time should be programmed to
PFD
Rev. A | Page 20 of 24
Phase Programmability
To program a specific RF output phase, change the phase word
in Register R1. As this word is swept from 0 to MOD, the RF output
phase sweeps over a 360
LOW FREQUENCY APPLICATIONS
The specification on the RF input is 0.5 GHz minimum; however,
lower RF frequencies can be used if the minimum slew rate
specification of 400 V/μs is met. An appropriate LVDS driver, such
as the FIN1001 from Fairchild Semiconductor, can be used to
square up the RF signal before it is fed back into the ADF4156
RF input.
FILTER DESIGN—ADIsimPLL
A filter design and analysis program is available to help implement
the PLL design. Visit
of the ADIsimPLL™ software. This software designs, simulates,
and analyzes the entire PLL frequency domain and time domain
response. Various passive and active filter architectures are allowed.
When designing the loop filter, keep the ratio of the PFD frequency
to the loop bandwidth >200:1 to attenuate the Σ-Δ modulator noise.
FREQUENCY
(Internal)
PHASE
SYNC
LE
–100
LAST CYCLE SLIP
0
Figure 24. Phase Resync Example
100
www.analog.com/pll
o
200
/MOD range in steps of 360
INCORRECT PHASE
300
PLL SETTLES TO
t
SYNC
400
TIME (µs)
500
600
for a free download
CORRECT PHASE
PLL SETTLES TO
AFTER RESYNC
700
800
o
/MOD.
900
1000