ADF7020-1BCPZ-RL7 Analog Devices Inc, ADF7020-1BCPZ-RL7 Datasheet - Page 29

• Manufacturer Part Number: ADF7020-1BCPZ-RL7
• Description: IC,RF Modulator/Demodulator,LLCC,48PIN,PLASTIC
• Manufacturer: Analog Devices Inc

Specifications of ADF7020-1BCPZ-RL7

• Design Resources: Low power, Long Range, ISM Wireless Measuring Node (CN0164)
• Frequency: 431MHz ~ 478MHz and 862MHz ~ 956MHz
• Data Rate - Maximum: 200kbps
• Modulation Or Protocol: ASK, FSK
• Applications: Data Transfer, RKE, Remote Control/Security Systems
• Power - Output: -16dBm ~ 13dBm
• Sensitivity: -119dBm
• Voltage - Supply: 2.3 V ~ 3.6 V
• Current - Receiving: 17.6mA
• Current - Transmitting: 21mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LFCSP
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Product Depth (mm): 7mm
• Product Length (mm): 7mm
• Operating Supply Voltage (min): 2.3V
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (max): 3.6V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-ADF7020-1DBZ8 - BOARD EVAL ADF7020-1 128-142MHZEVAL-ADF7020-1DBZ7 - BOARD EVAL ADF7020-1 310-340MHZEVAL-ADF7020-1DBZ6 - BOARD EVAL ADF7020-1 470-510MHZEVAL-ADF7020-1DBZ4 - BOARD EVAL ADF7020-1 405-435MHZEVAL-ADF7020-1DBZ5 - BOARD EVAL ADF7020-2 ADJ FREQ
• Memory Size: -
• Lead Free Status / Rohs Status: Compliant

SERIAL INTERFACE
The serial interface allows the user to program the eleven 32-bit
registers using a 3-wire interface (SCLK, SDATA, and SLE). It
consists of a voltage level shifter, a 32-bit shift register, and
11 latches. Signals should be CMOS compatible. The serial
interface is powered by the regulator and therefore is inactive
when CE is low.
Data is clocked into the register MSB first on the rising edge of
each clock (SCLK). Data is transferred to one of the 11 latches
on the rising edge of SLE. The destination latch is determined
by the value of the four control bits (C4 to C1). These are the
bottom 4 LSB, DB3 to DB0, as shown in the timing diagram in
Figure 2. Data can also be read back on the SREAD pin.
READBACK FORMAT
The readback operation is initiated by writing a valid control
word to the readback register and setting the readback-enable
bit (R7_DB8 = 1). The readback can begin after the control
word has been latched with the SLE signal. SLE must be kept
high while the data is read out. Each active edge at the SCLK
pin clocks the readback word out successively at the SREAD
pin, as shown in Figure 3, starting with the MSB first. The data
appearing at the first clock cycle following the latch operation
must be ignored.
AFC Readback
The AFC readback is valid only during the reception of FSK
signals with either the linear or correlator demodulator active.
The AFC readback value is formatted as a signed 16-bit integer
comprised of Bits RV1 to RV16 and is scaled according to the
following formula:
In the absence of frequency errors, the FREQ_RB value is equal
to the IF frequency of 200 kHz. Note that the down-converted
input signal must not fall outside the bandwidth of the analogue
IF filter for the AFC readback to yield a valid result. At low-
input signal levels, the variation in the readback value can be
improved by averaging.
FREQ_RB [Hz] = (AFC_READBACK × DEMOD_CLK)/2
BATTERY VOLTAGE/ADCIN/
TEMP. SENSOR READBACK
FILTER CAL READBACK
SILICON REVISION
READBACK MODE
RSSI READBACK
AFC READBACK
DB15
RV16
RV16
X
X
0
DB14
RV15
RV15
X
X
0
DB13
RV14
RV14
X
X
0
DB12
RV13
RV13
X
X
0
Figure 40. Readback Value Table
DB11
RV12
RV12
X
X
0
Rev. 0 | Page 29 of 48
15
DB10
RV11
RV11
LG2
X
0
RV10
RV10
DB9
LG1
X
0
READBACK VALUE
RSSI Readback
The RSSI readback operation yields valid results in Rx mode
with ASK or FSK signals. The format of the readback word is
shown in Figure 40. It is comprised of the RSSI level informa-
tion (Bits RV1 to RV7), the current filter gain (FG1, FG2), and
the current LNA gain (LG1, LG2) setting. The filter and LNA
gain are coded in accordance with the definitions in Register 9.
With the reception of ASK modulated signals, averaging of the
measured RSSI values improves accuracy. The input power can
be calculated from the RSSI readback value as outlined in the
RSSI/AGC.
Battery Voltage ADCIN/Temperature Sensor Readback
The battery voltage is measured at Pin VDD4. The readback
information is contained in Bits RV1 to RV7. This also applies
for the readback of the voltage at the ADCIN pin and the
temperature sensor. From the readback information, the battery
or ADCIN voltage can be determined using
Silicon Revision Readback
The silicon revision readback word is valid without setting any
other registers, especially directly after power-up. The silicon
revision word is coded with four quartets in BCD format. The
product code (PC) is coded with three quartets extending
from Bits RV5 to RV16. The revision code (RV) is coded with
one quartet extending from Bits RV1 to RV4. The product code
for the ADF7020-1 should read back as PC = 0x200. The
current revision code should read back as RC = 0x6.
Filter Calibration Readback
The filter calibration readback word is contained in Bits RV1 to
RV8 and is for diagnostic purposes only. Using the automatic
filter calibration function, accessible through Register 6, is
recommended. Before filter calibration is initiated Decimal 32
should be read back.
DB8
RV9
FG2
RV9
X
0
V
V
DB7
RV8
FG1
RV8
RV8
BATTERY
ADCIN
X
= (ADCIN_Voltage_Readback)/42.1
DB6
RV7
RV7
RV7
RV7
RV7
= (Battery_Voltage_Readback)/21.1
DB5
RV6
RV6
RV6
RV6
RV6
DB4
RV5
RV5
RV5
RV5
RV5
DB3
RV4
RV4
RV4
RV4
RV4
DB2
RV3
RV3
RV3
RV3
RV3
DB1
RV2
RV2
RV2
RV2
RV2
ADF7020-1
DB0
RV1
RV1
RV1
RV1
RV1