ADG406BPZ-REEL Analog Devices Inc, ADG406BPZ-REEL Datasheet - Page 11

• Manufacturer Part Number: ADG406BPZ-REEL
• Description: IC,ANALOG MUX,SINGLE,16-CHANNEL,CMOS,LDCC,28PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Series: LC²MOSr
• Type: Analog Multiplexerr

Specifications of ADG406BPZ-REEL

• Function: Multiplexer
• Circuit: 1 x 16:1
• On-state Resistance: 80 Ohm
• Voltage Supply Source: Single Supply
• Voltage - Supply, Single/dual (±): 5V, 12V
• Current - Supply: 100µA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-LCC (J-Lead)
• Package: 28PLCC
• Maximum On Resistance: 125@10.8V Ohm
• Maximum Propagation Delay Bus To Bus: 150@±15V|220@12V ns
• Maximum High Level Output Current: 20 mA
• Multiplexer Architecture: 16:1
• Maximum Turn-off Time: 180@12V ns
• Maximum Turn-on Time: 240@12V ns
• Power Supply Type: Single|Dual
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 8. Pin Function Descriptions
Pin No.
1
2
3
4 to 11
12
13
14 to 17
18
19 to 26
27
28
Table 9. Truth Table (ADG426)
A3
X
X
X
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
A2
X
X
X
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
Mnemonic
V
NC
RS
S16 to S9
GND
WR
A3 to A0
EN
S1 to S8
V
D
DD
SS
A1
X
X
X
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
Drain Terminal. This pin can be an input or an output.
Description
Most Positive Power Supply Potential.
No Connect.
Active Low Logic Input. When this pin is low, all switches are open, and address and enable latches registers are
cleared to 0.
Source Terminal 16 to Source Terminal 9. These pins can be inputs or outputs.
Ground (0 V) Reference.
The rising edge of the
Logic Control Input.
Active High Digital Input. When this pin is low, the device is disabled and all switches are turned off. When this pin
is high, the Ax logic inputs determine which switch is turned on.
Source Terminal 1 to Source Terminal 8. These pins can be inputs or outputs.
Most Negative Power Supply Potential. In single-supply applications, this pin can be connected to ground.
A0
X
X
X
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
EN
X
X
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
WR
X
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
WR
signal latches the state of the address control lines and the enable line.
GND
V
S16
S15
S14
S13
S12
S11
S10
WR
NC
RS
S9
A3
DD
Figure 10. 28-Lead PDIP/SSOP
RS
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
10
11
12
13
14
1
2
3
4
5
6
7
8
9
Rev. B | Page 11 of 20
NC = NO CONNECT
(Not to Scale)
ADG426
TOP VIEW
On switch
Retains previous switch condition
None (address and enable latches cleared)
None
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
28
27
26
25
24
23
22
21
20
19
18
17
16
15
D
V
S8
S7
S6
S5
S4
S3
S2
S1
EN
A0
A1
A2
SS
ADG406/ADG407/ADG426