ADG729BRU Analog Devices Inc, ADG729BRU Datasheet - Page 10

• Manufacturer Part Number: ADG729BRU
• Description: Analog Switch / Multiplexer (Mux) IC
• Manufacturer: Analog Devices Inc
• Type: Analog Multiplexerr

Specifications of ADG729BRU

• No. Of Channels: 8
• Analog Switch Case Style: TSSOP
• No. Of Pins: 16
• Peak Reflow Compatible (260 C): No
• Leakage Current: 0.01nA
• Leaded Process Compatible: No
• Mounting Type: Surface Mount
• Rohs Status: RoHS non-compliant
• Function: Multiplexer/Demultiplexer
• Circuit: 2 x 4:1
• On-state Resistance: 4.5 Ohm
• Voltage Supply Source: Single Supply
• Voltage - Supply, Single/dual (±): 2.7 V ~ 5.5 V
• Current - Supply: 10µA
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 16-TSSOP (0.173", 4.40mm Width)
• Package: 16TSSOP
• Maximum On Resistance: 11@3V Ohm
• Maximum High Level Output Current: 80 mA
• Multiplexer Architecture: 4:1
• Maximum Turn-off Time: 115(Typ)@3V ns
• Maximum Turn-on Time: 130(Typ)@3V ns
• Power Supply Type: Single
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

WRITE OPERATION
When writing to the ADG728/ADG729, the user must begin
with an address byte and R/W bit, after which the switch will
acknowledge that it is prepared to receive data by pulling SDA
low. This address byte is followed by the 8-bit word. The write
operations for each matrix switch are shown in the figures below.
READ OPERATION
When reading data back from the ADG728/ADG729, the user must begin with an address byte and R/W bit, after which the ma-
trix switch will acknowledge that it is prepared to transmit data by pulling SDA low. The readback operation is a single byte that
consists of the eight data bits in the input register. The read operations for each part are shown in Figures 18 and 19.
ADG728/ADG729
SCL
SCL
SCL
SCL
SDA
SDA
SDA
SDA
MASTER
MASTER
MASTER
MASTER
START
START
START
START
COND
COND
COND
COND
BY
BY
BY
BY
1
1
1
1
0
0
0
0
ADDRESS BYTE
ADDRESS BYTE
ADDRESS BYTE
ADDRESS BYTE
0
0
0
0
0
0
1
1
1
1
1
1
A1
A1
A1
A1
A0
A0
A0
A0
R/W
R/W
R/W
R/W
ADG728
ADG729
ADG728
ADG729
ACK
ACK
BY
BY
ACK
ACK
BY
BY
S8
S8
S8
S8
S7
S7
S7
S7
S6
S6
S6
S6
S5
S5
S5
S5
DATA BYTE
DATA BYTE
DATA BYTE
DATA BYTE
S4
S4
S4
S4
S3
S3
S3
S3
S2
S2
S2
S2
S1
S1
S1
S1
MASTER
MASTER
NO ACK
NO ACK
ADG728
ADG729
ACK
ACK
BY
BY
BY
BY
MASTER
MASTER
MASTER
MASTER
COND
COND
COND
COND
STOP
STOP
STOP
STOP
BY
BY
BY
BY