ADIS16364BMLZ Analog Devices Inc, ADIS16364BMLZ Datasheet - Page 9

• Manufacturer Part Number: ADIS16364BMLZ
• Description: Hi-Precision Tri-Axis Inertial Sensor
• Manufacturer: Analog Devices Inc
• Series: iSensor™r

Specifications of ADIS16364BMLZ

• Output Type: Digital - SPI
• Sensor Type: Gyroscope and Accelerometer
• No. Of Axes: 3
• Ic Interface Type: Serial
• Sensor Case Style: ML-24-2
• No. Of Pins: 24
• Supply Voltage Range: 4.75V To 5.25V
• Operating Temperature Range: -40°C To +105°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: ADIS16364/PCBZ - BOARD EVAL FOR ADIS16364
• Lead Free Status / Rohs Status: Compliant

THEORY OF OPERATION
BASIC OPERATION
The ADIS16364 is an autonomous sensor system that starts up
after it has a valid power supply voltage and begins producing
inertial measurement data at the factory default sample rate
setting of 819.2 SPS. After each sample cycle, the sensor data is
loaded into the output registers, and DIO1 pulses high, which
provides a new data ready control signal for driving system-level
interrupt service routines. In a typical system, a master processor
accesses the output data registers through the SPI interface, using
the connection diagram shown in Figure 9. Table 6 provides a
generic functional description for each pin on the master pro-
cessor. Table 7 describes the typical master processor settings
that are normally found in a configuration register and used for
communicating with the ADIS16364.
Table 6. Generic Master Processor Pin Names and Functions
Pin Name
SS
SCLK
MOSI
MISO
IRQ
Table 7. Generic Master Processor SPI Settings
Processor Setting
Master
SCLK Rate ≤ 2 MHz
SPI Mode 3
MSB First Mode
16-Bit Mode
1
For burst read, SCLK rate ≤ 1 MHz. For low power mode, SCLK rate ≤ 300 kHz.
SYSTEM
PROCESSOR
SPI MASTER
VDD
DOUT
Figure 9. Electrical Connection Diagram
SCLK
DIN
I/O LINES ARE COMPATIBLE WITH
CS
1
NOTES
1. THE DOUT BIT PATTERN REFLECTS THE ENTIRE CONTENTS OF THE REGISTER IDENTIFIED BY [A6:A0]
2. IF R/W = 1 DURING THE PREVIOUS SEQUENCE, DOUT IS NOT DEFINED.
SCLK
MOSI
MISO
3.3V OR 5V LOGIC LEVELS
IN THE PREVIOUS 16-BIT DIN SEQUENCE WHEN R/W = 0.
IRQ
SS
Function
Slave select
Serial clock
Master output, slave input
Master input, slave output
Interrupt request
Description
The ADIS16364 operates as a slave
Normal mode, SMPL_PRD[7:0] ≤ 0x09
CPOL = 1 (polarity), CPHA = 1 (phase)
Bit sequence
Shift register/data length
D15
R/W
D14
A6
D13
A5
6
3
5
4
7
CS
SCLK
DIN
DOUT
DIO1
D12
A4
10
13
ADIS16364
D11
A3
5V
SPI SLAVE
11
14
D10
A2
12
15
Figure 11. SPI Communication Bit Sequence
A1
D9
A0
D8
Rev. D | Page 9 of 20
DC7 DC6 DC5 DC4 DC3 DC2 DC1 DC0
D7
D6
The user registers provide addressing for all input/output
operations on the SPI interface. Each 16-bit register has two
7-bit addresses: one for its upper byte and one for its lower
byte. Table 8 lists the lower byte address for each register, and
Figure 10 shows the generic bit assignments.
READING SENSOR DATA
Although the ADIS16364 produces data independently, it
operates as a SPI slave device that communicates with system
(master) processors using the 16-bit segments displayed in
Figure 11. Individual register reads require two of these 16-bit
sequences. The first 16-bit sequence contains the read command
bit ( R /W = 0) and the target register address (A6 to A0); the last
eight bits are “don’t care” bits when requesting a read. The second
16-bit sequence transmits the register contents (D15 to D0) on
the DOUT line. For example, if DIN = 0x0A00, the contents of
the XACCL_OUT register are shifted out on the DOUT line
during the next 16-bit sequence.
The SPI operates in full-duplex mode, which means that the master
processor can read the output data from DOUT while using the
same SCLK pulses to transmit the next target address on DIN.
DEVICE CONFIGURATION
The user register memory map (see Table 8) identifies configu-
ration registers as either read/write or write only. Configuration
commands also use the bit sequence shown in Figure 11. If the
MSB = 1, the last eight bits (DC7 to DC0) in the DIN sequence
are loaded into the memory address associated with the address
bits (A6 to A0). For example, if DIN = 0xA11F, 0x1F is loaded
into Address 0x21 (XACCL_OFF, upper byte) at the conclusion
of the data frame.
The master processor initiates the backup function by setting
GLOB_CMD[3] = 1 (DIN = 0xBE04). This command copies
the user registers into their assigned flash memory locations
and requires the power supply to stay within its normal operating
range for the entire 50 ms process. The FLASH_CNT register
provides a running count of these events for monitoring the
long-term reliability of the flash memory.
D5
15
D4
14
13
D3
UPPER BYTE
12
Figure 10. Generic Register Bit Assignments
D2
11
D1
10
D0
9
8
7
D15
R/W
6
D14
A6
5
LOWER BYTE
D13
4
A5
ADIS16364
3
2
1
0