ADM8690AN Analog Devices Inc, ADM8690AN Datasheet - Page 7

• Manufacturer Part Number: ADM8690AN
• Description: IMPROVED ADM690
• Manufacturer: Analog Devices Inc
• Type: Battery Backup Circuitr

Specifications of ADM8690AN

• Rohs Compliant: NO
• Rohs Status: RoHS non-compliant
• Number Of Voltages Monitored: 1
• Output: Push-Pull, Totem Pole
• Reset: Active Low
• Reset Timeout: 35 ms Minimum
• Voltage - Threshold: 4.65V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Through Hole
• Package / Case: 8-DIP (0.300", 7.62mm)

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Table 4. Pin Function Descriptions
Mnemonic
V
V
V
GND
RESET
WDI
PFI
PFO
CE
CE
BATT ON
LOW LINE
RESET
OSC SEL
OSC IN
WDO
CC
BATT
OUT
IN
OUT
Figure 3. ADM8690, ADM8692, and ADM8694
Function
Ground. This is the 0 V ground reference for all signals.
Power Supply Input. 5 V nominal.
Backup Battery Input.
Output Voltage. V
100 mA to power CMOS RAM. Connect V
Logic Output. RESET goes low if V
period. The reset threshold is typically 4.65 V for the ADM8690/ADM8691/ADM8694/ADM8695 and 4.4 V for the ADM8692
and ADM8693. RESET remains low for 50 ms (ADM8690/ADM8691/ADM8692/ADM8693) or 200 ms (ADM8694/ADM8695)
after V
(ADM8694/ADM8695) if the watchdog timer is enabled but not serviced within its timeout period. The RESET pulse width can
be adjusted on the ADM8691/ADM8693/ADM8695, as shown in Table 5. The RESET output has an internal 3 μA pull-up, and
can either connect to an open collector reset bus or directly drive a CMOS gate without an external pull-up resistor.
Watchdog Input. WDI is a three-level input. If WDI remains either high or low for longer than the watchdog timeout period,
RESET pulses low and WDO goes low. The timer resets with each transition on the WDI line. The watchdog timer can be
disabled if WDI is left floating or is driven to midsupply.
Power-Fail Input. PFI is the noninverting input to the power-fail comparator. When PFI is less than 1.3 V, PFO goes low.
Connect PFI to GND or V
Power-Fail Output. PFO is the output of the power-fail comparator. It goes low when PFI is less than 1.3 V. The comparator is
turned off and PFO goes low when V
Logic Input. The input to the CE gating circuit. When not in use, connect this pin to GND or V
Logic Output. CE
the reset threshold, CE
Logic Output. BATT ON goes high when V
switched to V
output current above the 100 mA rating of V
Logic Output. LOW LINE goes low when V
threshold.
Logic Output. RESET is an active high output. It is the inverse of RESET.
Logic Oscillator Select Input. When OSC SEL is unconnected (floating) or driven high, the internal oscillator sets the reset
active time and watchdog timeout period. When OSC SEL is low, the external oscillator input, OSC IN, is enabled. OSC SEL has
a 3 μA internal pull-up (see Table 5).
Oscillator Logic Input. With OSC SEL low, OSC IN can be driven by an external clock signal or an external capacitor can be
connected between OSC IN and GND. This sets both the reset active pulse timing and the watchdog timeout period (see
Table 5 and Figure 17, Figure 18, Figure 19, and Figure 20). With OSC SEL high or floating, the internal oscillator is enabled and
the reset active time is fixed at 50 ms typical (ADM8691/ADM8693) or 200 ms typical (ADM8695). In this mode, the OSC IN pin
selects between fast (100 ms) and slow (1.6 s) watchdog timeout periods. In both modes, the timeout period immediately
after a reset is 1.6 s typical.
Logic Output. The watchdog output, WDO, goes low if WDI remains either high or low for longer than the watchdog timeout
period. WDO is set high by the next transition at WDI. If WDI is unconnected or at midsupply, the watchdog timer is disabled
and WDO remains high. WDO also goes high when LOW LINE goes low.
V
GND
V
OUT
PFI
CC
CC
1
2
3
4
returns above the threshold. RESET also goes low for 50 ms (ADM8690/ADM8691/ADM8692/ADM8693) or 200 ms
Pin Configuration
ADM8690/
ADM8692/
(Not to Scale)
ADM8694
TOP VIEW
CC
. The output typically sinks 35 mA and can directly drive the base of an external PNP transistor to increase the
OUT
CC
or V
is a gated version of the CE
OUT
8
7
6
5 PFO
BATT
OUT
V
RESET
WDI
is forced high. See Figure 21 and Figure 22.
BATT
is internally switched to V
when not used.
ADM8690/ADM8691/ADM8692/ADM8693/ADM8694/ADM8695
CC
falls below the reset threshold, or the watchdog timer is not serviced within its timeout
CC
is below V
OUT
OUT
CC
falls below the reset threshold. It returns high as soon as V
to V
OUT
is internally switched to the V
IN
.
Rev. A | Page 7 of 20
CC
BATT
signal. CE
if V
.
OUT
OUT
, depending on which is at the highest potential. V
and V
OUT
tracks CE
BATT
are not used.
IN
when V
Figure 4. ADM8691, ADM8693, and ADM8695
BATT
LOW LINE
BATT ON
OSC SEL
input. It goes low when V
OSC IN
V
CC
V
BATT
GND
V
OUT
is above the reset threshold. If V
CC
1
2
3
4
5
6
7
8
Pin Configuration
ADM8691/
ADM8693/
(Not to Scale)
ADM8695
TOP VIEW
OUT
.
16
15
14
13
12
11
10
9
CC
RESET
RESET
WDO
CE
CE
WDI
PFO
PFI
OUT
rises above the reset
IN
OUT
OUT
is internally
can supply up to
CC
is below