ADM9690ARNZ-REEL Analog Devices Inc, ADM9690ARNZ-REEL Datasheet - Page 5

• Manufacturer Part Number: ADM9690ARNZ-REEL
• Description: SUPERVISOR WITH 2 RESETS I.C.
• Manufacturer: Analog Devices Inc
• Type: Watchdog Circuitr

Specifications of ADM9690ARNZ-REEL

• Number Of Voltages Monitored: 1
• Output: Push-Pull, Totem Pole
• Reset: Active Low
• Reset Timeout: 10 ms, 50 ms Typical
• Voltage - Threshold: 4.31V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

POWER SUPPLY AND WATCHDOG MONITORING
CIRCUIT
The ADM9690 contains a power supply voltage monitoring
comparator and a watchdog timer monitor. Either V
ping outside tolerance or the watchdog timer timing out results
in a reset sequence as discussed below. Two reset outputs are
provided. RESET(1) and RESET(2).
POWER FAIL/POWER-ON RESET
When V
outputs are forced low immediately.
On power-up, RESET(1) will remain low for 50 milliseconds
after V
power-on reset for the microprocessor. RESET(2) remains
active low for an additional 10 ms. RESET(1) is intended to
REV. A
WATCHDOG
INPUT (WDI)
OSC SEL1
MON
OSC SEL2
MON
RESET(1)
RESET(2)
V
MON
rises above the reset threshold. This provides a
falls below the reset threshold (4.4 V) both RESET
Figure 6. Functional Block Diagram
V
Figure 7. Power-On RESET Timing
MON
4.31V
WATCHDOG
WATCHDOG
TRANSITION
TIMEBASE
DETECTOR
t
1
V
CC
GND
RESET(1)
RESET(2)
TIMER
TIMER
ADM9690
t
2
MON
RESET(1)
RESET(2)
drop-
–5–
provide a power-on reset signal for the µP while RESET(2) is
used to hold additional circuitry in a reset state until the µP has
regained control following a power-up.
The guaranteed minimum and maximum thresholds for the
ADM9690 are 4.3 V and 4.5 V.
Watchdog Timer RESET
The watchdog timer circuit monitors the activity of the micro-
processor in order to check that it is not stalled in an infinite
loop. An output line on the processor may be used to toggle the
Watchdog Input (WDI) line. If this line is not toggled within the
selected timeout period, both RESET outputs are taken active
(low). RESET(1) remains low for 50 ms and RESET(2) re-
mains low for an additional 10 ms . Each transition (either
positive-going or negative-going) of WDI after RESET(1) has
gone inactive restarts the watchdog timer. The actual watchdog
timeout period is adjustable using SEL1 and SEL2. Four timeout
periods are selectable. Please refer to Table I.
The watchdog timer is restarted at the end of RESET(1)
(RESET(1) going high), whether the reset was caused by lack of
activity on WDI or by V
SEL2
0
0
1
1
RESET(1)
RESET(2)
WDI
Figure 8. Watchdog RESET Timing
0
1
0
1
SEL1
t
WD
MON
Table I.
falling below the reset threshold.
t
1
Watchdog Timeout
Period t
0.75
1.5
12.5
25
ADM9690
WD
t
2
(ms)