ADN2811ACPZ-CML Analog Devices Inc, ADN2811ACPZ-CML Datasheet - Page 18

• Manufacturer Part Number: ADN2811ACPZ-CML
• Description: S/Rate 2.5/2.7Gbps CDR/ PA Low Power I.C
• Manufacturer: Analog Devices Inc
• Type: Clock and Data Recovery (CDR)r

Specifications of ADN2811ACPZ-CML

• Output: CML
• Frequency - Max: 2.7GHz
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-LFCSP
• Frequency-max: 2.7GHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Input: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADN2811
DC-COUPLED APPLICATION
The inputs to the ADN2811 can also be dc-coupled. This may
be necessary in burst mode applications where there are long
periods of CIDs and baseline wander cannot be tolerated. If the
inputs to the ADN2811 are dc-coupled, care must be taken not
to violate the input range and common-mode level
requirements of the ADN2811 (see Figure 23, Figure 24, and
Figure 25). If dc-coupling is required and the output levels of
the TIA do not adhere to the levels shown in Figure 24 and
Figure 25, there needs to be level shifting and/or an attenuator
between the TIA outputs and the ADN2811 inputs.
LOL TOGGLING DURING LOSS OF INPUT DATA
If the input data stream is lost due to a break in the optical link
(or for any reason), the clock output from the ADN2811 stays
within 1000 ppm of the VCO center frequency as long as there
is a valid reference clock. The LOL pin toggles at a rate of
several kHz because the LOL pin toggles between a Logic 1 and
a Logic 0 while the frequency loop and phase loop swap control
of the VCO. The chain of events is as follows:
•
•
•
•
•
The input data stream is lost due to a break in the link. The
VCO frequency drifts until the frequency error is greater
than 1000 ppm. LOL is asserted to a Logic 1 as control of
the VCO is passed back to the frequency loop.
The frequency loop pulls the VCO to within 500 ppm of its
center frequency. Control of the VCO is passed back to the
phase loop and LOL is deasserted to a Logic 0.
The phase loop tries to acquire, but there is no input data
present so the VCO frequency drifts.
The VCO frequency drifts until the frequency error is
greater than 1000 ppm. LOL is asserted to a Logic 1 as
control of the VCO is passed back to the frequency loop.
This process is repeated until a valid input data stream is
re-established.
The ADN2811 is locked to the input data stream; LOL = 0.
Rev. B | Page 18 of 20
INPUT (V)
INPUT (V)
PIN
NIN
PIN
NIN
VCC
Figure 25. Maximum Allowed DC-Coupled Input Levels
Figure 24. Minimum Allowed DC-Coupled Input Levels
V p-p = PIN – NIN = 2 × V
V p-p = PIN – NIN = 2 × V
Figure 23. ADN2811 with DC-Coupled Inputs
TIA
0.1µ F
50Ω
50Ω
SE
SE
= 2.4V MAX
PIN
NIN
= 10mV AT SENSITIVITY
VREF
ADN2811
V
50Ω
SE
V
SE
= 1.2V MAX
= 5mV MIN
50Ω
V
(DC-COUPLED)
V
(DC-COUPLED)
CM
CM
= 0.4V MIN
= 0.6V