ADN8102ACPZ Analog Devices Inc, ADN8102ACPZ Datasheet - Page 5

• Manufacturer Part Number: ADN8102ACPZ
• Description: IC,Cable Equalizer,LLCC,64PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Series: XStream™r

Specifications of ADN8102ACPZ

• Applications: Ethernet Controller
• Interface: I²C
• Voltage - Supply: 1.8 V ~ 3.3 V
• Package / Case: 64-LFCSP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

TIMING SPECIFICATIONS
Table 2. I
Parameter
f
t
t
t
t
t
t
t
t
t
t
C
t
1
SCL
HD:STA
SU:STA
LOW
HIGH
HD:DAT
SU:DAT
R
F
SU:STO
BUF
RESET
Reset pulse width is defined as the time RESET is held below the logic low threshold (V
IO
SDA
SCL
t
F
2
C Timing Parameters
S
Min
0
0.6
0.6
1.3
0.6
0
10
1
1
0.6
1
5
10
t
HD:STA
t
LOW
t
HD:DAT
Max
400
Not applicable
Not applicable
Not applicable
Not applicable
Not applicable
Not applicable
300
300
Not applicable
Not applicable
7
Not applicable
t
t
SU:DAT
R
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
t
0
HIGH
DVCC MAX LIMIT
DVCC MIN LIMIT
DVCC (V)
5
t
Unit
kHz
μs
μs
μs
μs
μs
ns
ns
ns
μs
ns
pF
ns
F
10
Figure 3. Reset Timing Diagram
Figure 2. I
15
Rev. B | Page 5 of 36
t
SU:STA
2
20
Description
SCL clock frequency
Hold time for a start condition
Setup time for a repeated start condition
Low period of the SCL clock
High period of the SCL clock
Data hold time
Data setup time
Rise time for both SDA and SCL
Fall time for both SDA and SCL
Setup time for a stop condition
Bus free time between a stop and a start condition
Capacitance for each I/O pin
Reset pulse width
C Timing Diagram
TIME (ns)
25
IL
RESET
) listed in Table 1 while the DV
t
RESET
Sr
30
35
t
HD:STA
1
40
45
50
CC
supply is within the operating range in Table 1.
t
SU:STO
t
R
P
t
BUF
ADN8102
S