ADP1871ACPZ-0.3-R7 Analog Devices Inc, ADP1871ACPZ-0.3-R7 Datasheet - Page 34
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ADP1871ACPZ-0.3-R7
Manufacturer Part Number
ADP1871ACPZ-0.3-R7
Description
300kHz, Light Load Eff Enabled
Manufacturer
Analog Devices Inc
Datasheet
1.ADP1870-0.3-EVALZ.pdf
(44 pages)
Specifications of ADP1871ACPZ-0.3-R7
Frequency - Max
300kHz
Pwm Type
Current Mode
Number Of Outputs
1
Duty Cycle
84%
Voltage - Supply
2.95 V ~ 20 V
Buck
Yes
Boost
No
Flyback
No
Inverting
No
Doubler
No
Divider
No
Cuk
No
Isolated
No
Operating Temperature
-40°C ~ 125°C
Package / Case
10-WFDFN, CSP Exposed Pad
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
ADP1871ACPZ-0.3-R7
ADP1871ACPZ-0.3-R7TR
ADP1871ACPZ-0.3-R7TR
ADP1870/ADP1871
SEPARATE ANALOG GROUND
PLANE FOR THE ANALOG
COMPONENTS (THAT IS,
COMPENSATION AND
FEEDBACK RESISTORS).
BYPASS POWER CAPACITOR (C1)
FOR VREG BIAS DECOUPLING
AND HIGH FREQUENCY
CAPACITOR (C2) AS CLOSE AS
POSSIBLE TO THE IC.
SENSITIVE ANALOG
COMPONENTS
LOCATED FAR
FROM THE NOISY
POWER SECTION.
INPUT CAPACITORS
ARE MOUNTED CLOSE
TO DRAIN OF Q1/Q2
AND SOURCE OF Q3/Q4.
Figure 86. Overall Layout of the ADP1870 High Current Evaluation Board
Rev. A | Page 34 of 44
OUTPUT CAPACITORS
ARE MOUNTED ON THE
RIGHTMOST AREA OF
THE EVB, WRAPPING
BACK AROUND TO THE
MAIN POWER GROUND
PLANE, WHERE IT MEETS
WITH THE NEGATIVE
TERMINALS OF THE
INPUT CAPACITORS