ADSP-21061LKSZ-160 Analog Devices Inc, ADSP-21061LKSZ-160 Datasheet - Page 40

• Manufacturer Part Number: ADSP-21061LKSZ-160
• Description: ADSP-21061 1MBIT,40MHz, 3v SHARC/pb-free
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Floating Pointr

Specifications of ADSP-21061LKSZ-160

• Interface: Synchronous Serial Port (SSP)
• Clock Rate: 40MHz
• Non-volatile Memory: External
• On-chip Ram: 128kB
• Voltage - I/o: 3.30V
• Voltage - Core: 3.30V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 240-MQFP, 240-PQFP
• Device Core Size: 32b
• Architecture: Super Harvard
• Format: Floating Point
• Clock Freq (max): 40MHz
• Mips: 40
• Device Input Clock Speed: 40MHz
• Ram Size: 128KB
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.15V
• Operating Supply Voltage (max): 3.45V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: MQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADSP-21061/ADSP-21061L
Table 25. Serial Ports—Internal Clock
1
Table 26. Serial Ports—Enable and Three-State
1
2
Table 27. Serial Ports—External Late Frame Sync
1
Parameter
Switching Characteristics
t
t
t
t
t
Parameter
Switching Characteristics
t
t
t
t
t
t
Parameter
Switching Characteristics
t
t
Referenced to drive edge.
Referenced to drive edge.
For the ADSP-21061L (3.3 V), this specification is 3.5 ns min.
MCE = 1, TFS enable and TFS valid follow t
DFSI
HOFSI
DDTI
HDTI
SCLKIW
DDTEN
DDTTE
DDTIN
DDTTI
DCLK
DPTR
DDTLFSE
DDTENFS
TFS Delay After TCLK (Internally Generated TFS)
TFS Hold After TCLK (Internally Generated TFS)
Transmit Data Delay After TCLK
Transmit Data Hold After TCLK
TCLK/RCLK Width
Data Delay from Late External TFS or External RFS with MCE = 1, MFD = 0
Data Enable from Late FS or MCE = 1, MFD = 0
Data Enable from External TCLK
Data Disable from External TCLK
Data Enable from Internal TCLK
Data Disable from Internal TCLK
TCLK/RCLK Delay from CLKIN
SPORT Disable After CLKIN
DDTLFSE
and t
DDTENFS
.
1
1
Rev. C | Page 40 of 56 | July 2007
1
1, 2
1
1
1
1
1
1
Min
–1.5
0
t
SCLK
Min
4.5
0
Min
3.5
/2 –1.5
5 V and 3.3 V
5 V and 3.3 V
5 V and 3.3 V
Max
4.5
7.5
t
Max
10.5
3
22 + 3DT/8
17
SCLK
Max
12
/2+1.5
Unit
ns
ns
ns
ns
ns
Unit
ns
ns
ns
ns
ns
ns
Unit
ns
ns