ADSP-21065LCSZ-240 Analog Devices Inc, ADSP-21065LCSZ-240 Datasheet - Page 7

• Manufacturer Part Number: ADSP-21065LCSZ-240
• Description: ADSP-21065L 60 Mhz
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Fixed/Floating Pointr

Specifications of ADSP-21065LCSZ-240

• Interface: Host Interface, Serial Port
• Clock Rate: 60MHz
• Non-volatile Memory: External
• On-chip Ram: 64kB
• Voltage - I/o: 3.30V
• Voltage - Core: 3.30V
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 208-MQFP, 208-PQFP
• Device Core Size: 32b
• Architecture: Enhanced Harvard
• Format: Floating Point
• Clock Freq (max): 60MHz
• Mips: 60
• Device Input Clock Speed: 60MHz
• Ram Size: 68KB
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.13V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 208
• Package Type: MQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ADS-P21065LCSZ240; ADS-P21065LCSZ240

PIN DESCRIPTIONS
ADSP-21065L pin definitions are listed below. Inputs identified as synchronous (S) must meet timing requirements with respect to
CLKIN (or with respect to TCK for TMS, TDI). Inputs identified as asynchronous (A) can be asserted asynchronously to CLKIN
(or to TCK for TRST).
Unused inputs should be tied or pulled to VDD or GND, except for ADDR
internal pull-up or pull-down resistors (CPA, ACK, DTxX, DRxX, TCLKx, RCLKx, TMS, and TDI)—these pins can be left float-
ing. These pins have a logic-level hold circuit that prevents the input from floating internally.
I = Input
O = Output
T = Three-state (when SBTS is asserted, or when the ADSP-2106x is a bus slave)
Pin
ADDR
DATA
MS
RD
WR
SW
ACK
SBTS
IRQ
FLAG
REV. C
3-0
2-0
11-0
31-0
23-0
Type
I/O/T
I/O/T
I/O/T
I/O/T
I/O/T
I/O/T
I/O/S
I/S
I/A
I/O/A
Function
External Bus Address. The ADSP-21065L outputs addresses for external memory and
peripherals on these pins. In a multiprocessor system the bus master outputs addresses for read/
writes of the IOP registers of the other ADSP-21065L. The ADSP-21065L inputs addresses
when a host processor or multiprocessing bus master is reading or writing its IOP registers.
External Bus Data. The ADSP-21065L inputs and outputs data and instructions on these
pins. The external data bus transfers 32-bit single-precision floating-point data and 32-bit fixed-
point data over bits 31-0. 16-bit short word data is transferred over bits 15-0 of the bus. Pull-up
resistors on unused DATA pins are not necessary.
Memory Select Lines. These lines are asserted as chip selects for the corresponding banks of
external memory. Internal ADDR
memory address lines that change at the same time as the other address lines. When no external
memory access is occurring the MS
tional memory access instruction is executed, whether or not the condition is true. Additionally,
an MS
active. In a multiprocessor system, the MS
Memory Read Strobe. This pin is asserted when the ADSP-21065L reads from external memory
devices or from the IOP register of another ADSP-21065L. External devices (including another
ADSP-21065L) must assert RD to read from the ADSP-21065L’s IOP registers. In a multipro-
cessor system, RD is output by the bus master and is input by another ADSP-21065L.
Memory Write Strobe. This pin is asserted when the ADSP-21065L writes to external memory
devices or to the IOP register of another ADSP-21065L. External devices must assert WR to
write to the ADSP-21065L’s IOP registers. In a multiprocessor system, WR is output by the bus
master and is input by the other ADSP-21065L.
Synchronous Write Select. This signal interfaces the ADSP-21065L to synchronous memory
devices (including another ADSP-21065L). The ADSP-21065L asserts SW to provide an early
indication of an impending write cycle, which can be aborted if WR is not later asserted (e.g., in
a conditional write instruction). In a multiprocessor system, SW is output by the bus master and
is input by the other ADSP-21065L to determine if the multiprocessor access is a read or write.
SW is asserted at the same time as the address output.
Memory Acknowledge. External devices can deassert ACK to add wait states to an external
memory access. ACK is used by I/O devices, memory controllers, or other peripherals to hold
off completion of an external memory access. The ADSP-21065L deasserts ACK as an output
to add wait states to a synchronous access of its IOP registers. In a multiprocessor system, a
slave ADSP-21065L deasserts the bus master’s ACK input to add wait state(s) to an access of
its IOP registers. The bus master has a keeper latch on its ACK pin that maintains the input at
the level to which it was last driven.
Suspend Bus Three-State. External devices can assert SBTS to place the external bus address,
data, selects, and strobes—but not SDRAM control pins—in a high impedance state for the
following cycle. If the ADSP-21065L attempts to access external memory while SBTS is as-
serted, the processor will halt and the memory access will not finish until SBTS is deasserted.
SBTS should only be used to recover from host processor/ADSP-21065L deadlock.
Interrupt Request Lines. May be either edge-triggered or level-sensitive.
Flag Pins. Each is configured via control bits as either an input or an output. As an input, it can
be tested as a condition. As an output, it can be used to signal external peripherals.
S = Synchronous
A = Asynchronous
3-0
line which is mapped to SDRAM may be asserted even when no SDRAM access is
–7–
P = Power Supply
G = Ground
25-24
3-0
are decoded into MS
lines are inactive; they are active, however, when a condi-
23-0,
DATA
3-0
lines are output by the bus master.
31-0
, FLAG
3-0
11-0
. The MS
, SW, and inputs that have
(O/D) = Open Drain
(A/D) = Active Drive
ADSP-21065L
3-0
lines are decoded