ADSP-21065LKCA-240 Analog Devices Inc, ADSP-21065LKCA-240 Datasheet - Page 34

• Manufacturer Part Number: ADSP-21065LKCA-240
• Description: Digital Signal Processor IC
• Manufacturer: Analog Devices Inc
• Series: SHARCr
• Type: Fixed/Floating Pointr

Specifications of ADSP-21065LKCA-240

• Dsp Type: Fixed / Floating Point
• Package/case: 196-CSPBGA
• Frequency: 66MHz
• Leaded Process Compatible: No
• Peak Reflow Compatible (260 C): No
• Supply Voltage Max: 3.6V
• Rohs Status: RoHS non-compliant
• Interface: Host Interface, Serial Port
• Clock Rate: 60MHz
• Non-volatile Memory: External
• On-chip Ram: 64kB
• Voltage - I/o: 3.30V
• Voltage - Core: 3.30V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 196-CSPBGA
• Device Core Size: 32b
• Architecture: Enhanced Harvard
• Format: Floating Point
• Clock Freq (max): 60MHz
• Mips: 60
• Device Input Clock Speed: 60MHz
• Ram Size: 68KB
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.13V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: CSPBGA
• Package: 196CSP-BGA
• Numeric And Arithmetic Format: Floating-Point
• Maximum Speed: 60 MHz
• Device Million Instructions Per Second: 60 MIPS
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: ADSP-21065LKCA240

ADSP-21065L
RCLK
TCLK
EXTERNAL RFS with MCE = 1, MFD = 0
LATE EXTERNAL TFS
RFS
TFS
Figure 21. External Late Frame Sync (Frame Sync Setup < t
Figure 22. External Late Frame Sync (Frame Sync Setup > t
DT
DT
EXTERNAL RFS with MCE = 1, MFD = 0
LATE EXTERNAL TFS
RCLK
TCLK
RFS
TFS
DT
DT
DRIVE
DRIVE
DRIVE
DRIVE
t
t
t
t
DDTLFSE
DDTLFSE
DDTLSCK
DDTLSCK
t
t
SFSE/I
SFSE/I
t
t
SFSE/I
t
SFSE/I
t
t
t
DTENLFSE
DTENLSCK
DTENLSCK
DTENLFSE
SAMPLE
SAMPLE
SAMPLE
SAMPLE
1ST BIT
1ST BIT
1ST BIT
1ST BIT
DRIVE
DRIVE
–34–
t
t
t
t
HOFSE/I
HOFSE/I
HDTE/I
HDTE/I
DRIVE
DRIVE
t
t
DDTE/I
DDTE/I
t
t
HOFSE/I
HOFSE/I
t
t
HDTE/I
HDTE/I
t
t
DDTE/I
DDTE/I
2ND BIT
2ND BIT
2ND BIT
2ND BIT
SCLK
SCLK
/2)
/2)
REV. C