ADSP-21160MKBZ-80 Analog Devices Inc, ADSP-21160MKBZ-80 Datasheet - Page 30

• Manufacturer Part Number: ADSP-21160MKBZ-80
• Description: 32bit SHARC W/SIMD Capability
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Floating Pointr

Specifications of ADSP-21160MKBZ-80

• Interface: Host Interface, Link Port, Serial Port
• Clock Rate: 80MHz
• Non-volatile Memory: External
• On-chip Ram: 512kB
• Voltage - I/o: 3.30V
• Voltage - Core: 2.50V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 400-BGA
• Device Core Size: 32b
• Architecture: Enhanced Harvard
• Format: Floating Point
• Clock Freq (max): 80MHz
• Mips: 80
• Device Input Clock Speed: 80MHz
• Ram Size: 512KB
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (min): 2.37/3.13V
• Operating Supply Voltage (max): 2.63/3.47V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 400
• Package Type: BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

ADSP-21160M
Three-State Timing—Bus Master and Bus Slave
These specifications show how the memory interface is
disabled (stops driving) or enabled (resumes driving)
relative to CLKIN and the SBTS pin. This timing is appli-
cable to bus master transition cycles (BTC) and host
transition cycles (HTC) as well as the SBTS pin.
Table 16. Three-State Timing—Bus Slave, HBR, SBTS
1
2
3
Strobes = RDx, WRx, DMAGx.
In addition to bus master transition cycles, these specs also apply to bus master and bus slave synchronous read/write.
Memory Interface = Address, RDx, WRx, MSx, PAGE, DMAGx, and BMS (in EPROM boot mode).
Parameter
Timing Requirements:
t
t
Switching Characteristics:
t
t
t
t
t
t
t
t
t
t
t
t
t
t
STSCK
HTSCK
MIENA
MIENS
MIENHG
MITRA
MITRS
MITRHG
DATEN
DATTR
ACKEN
ACKTR
CDCEN
CDCTR
MTRHBG
MENHBG
SBTS Setup Before CLKIN
SBTS Hold After CLKIN
Address/Select Enable After CLKIN
Strobes Enable After CLKIN
HBG Enable After CLKIN
Address/Select Disable After CLKIN
Strobes Disable After CLKIN
HBG Disable After CLKIN
Data Enable After CLKIN
Data Disable After CLKIN
ACK Enable After CLKIN
ACK Disable After CLKIN
CLKOUT Enable After CLKIN
CLKOUT Disable After CLKIN
Memory Interface Disable Before HBG
Low
Memory Interface Enable After HBG
High
3
3
2
2
2
2
1
1
–30–
Min
6
1
1.5
1.5
1.5
0.25t
0.25t
3.5
1.5
1.5
1.5
1.5
1.5
t
t
t
CCLK
CK
CK
– 6
– 5
– 3
CCLK
CCLK
– 1
– 4
Max
9
9
9
0.25t
0.25t
8
10
5
9
5
9
t
t
t
CCLK
CK
CK
+2
+5
+1
CCLK
CCLK
+4
REV. 0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns