ADSP-2185MKSTZ-300 Analog Devices Inc, ADSP-2185MKSTZ-300 Datasheet - Page 25
![75mhz,16k/16k, 2.5v, Lqfp](/photos/6/59/65915/st-100_sml.jpg)
ADSP-2185MKSTZ-300
Manufacturer Part Number
ADSP-2185MKSTZ-300
Description
75mhz,16k/16k, 2.5v, Lqfp
Manufacturer
Analog Devices Inc
Series
ADSP-21xxr
Type
Fixed Pointr
Datasheet
1.ADSP-2185MBSTZ-266.pdf
(40 pages)
Specifications of ADSP-2185MKSTZ-300
Interface
Host Interface, Serial Port
Clock Rate
75MHz
Non-volatile Memory
External
On-chip Ram
80kB
Voltage - I/o
3.30V
Voltage - Core
2.50V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
100-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
ADSP-2185MKSTZ300
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ADSP-2185MKSTZ-300
Manufacturer:
Analog Devices Inc
Quantity:
10 000
Part Number:
ADSP-2185MKSTZ-300
Manufacturer:
ADI/亚德诺
Quantity:
20 000
Parameter
Bus Request–Bus Grant
Timing Requirements:
t
t
Switching Characteristics:
t
t
t
t
t
t
NOTES
xMS = PMS, DMS, CMS, IOMS, BMS.
1
2
BH
BS
SD
SDB
SE
SEC
SDBH
SEH
BR is an asynchronous signal. If BR meets the setup/hold requirements, it will be recognized during the current clock cycle; otherwise the signal will be recognized on
the following cycle. Refer to the ADSP-2100 Family User’s Manual for BR/BG cycle relationships.
BGH is asserted when the bus is granted and the processor or BDMA requires control of the bus to continue.
BR Hold after CLKOUT High
BR Setup before CLKOUT Low
CLKOUT High to xMS, RD, WR Disable
xMS, RD, WR Disable to BG Low
BG High to xMS, RD, WR Enable
xMS, RD, WR Enable to CLKOUT High
xMS, RD, WR Disable to BGH Low
BGH High to xMS, RD, WR Enable
PMS, DMS
BMS, RD
CLKOUT
CLKOUT
BGH
WR
BG
BR
t
SD
t
1
BH
1
t
t
BS
t
SDBH
SDB
2
2
Min
0.25t
0.25t
0
0
0.25t
0
0
t
t
SEH
SE
CK
CK
CK
t
– 3
+ 2
+ 10
SEC
ADSP-2185M
Max
0.25t
CK
+ 8
Unit
ns
ns
ns
ns
ns
ns
ns
ns