ADSP-BF514BBCZ-4F4 Analog Devices Inc, ADSP-BF514BBCZ-4F4 Datasheet - Page 38

• Manufacturer Part Number: ADSP-BF514BBCZ-4F4
• Description: Low-Pwr BF Proc W/flash & Cnsmr Conctvty
• Manufacturer: Analog Devices Inc
• Series: Blackfin®r
• Type: Fixed Pointr

Specifications of ADSP-BF514BBCZ-4F4

• Interface: I²C, PPI, RSI, SPI, SPORT, UART/USART
• Clock Rate: 400MHz
• Non-volatile Memory: FLASH (4Mbit)
• On-chip Ram: 116kB
• Voltage - I/o: 1.8V, 2.5V, 3.3V
• Voltage - Core: 1.30V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 168-LFBGA
• Architecture: Modified Harvard
• Format: Fixed Point
• Clock Freq (max): 400MHz
• Device Input Clock Speed: 400MHz
• Ram Size: 48KB
• Program Memory Size: 1024KB
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Package: 168CSP-BGA
• Numeric And Arithmetic Format: Fixed-Point
• Maximum Speed: 400 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F
Parallel Peripheral Interface Timing
Table 33
Figure 24 on Page 45
operations.
Table 33. Parallel Peripheral Interface Timing
Parameter
Timing Requirements
t
t
Timing Requirements - GP Input and Frame Capture Modes
t
t
t
t
Switching Characteristics - GP Output and Frame Capture Modes
t
t
t
t
PCLKW
PCLK
SFSPE
HFSPE
SDRPE
HDRPE
DFSPE
HOFSPE
DDTPE
HDTPE
and
Figure 15 on Page
PPI_CLK Width
PPI_CLK Period
External Frame Sync Setup Before PPI_CLK
(Nonsampling Edge for Rx, Sampling Edge for Tx)
External Frame Sync Hold After PPI_CLK
Receive Data Setup Before PPI_CLK
Receive Data Hold After PPI_CLK
Internal Frame Sync Delay After PPI_CLK
Internal Frame Sync Hold After PPI_CLK
Transmit Data Delay After PPI_CLK
Transmit Data Hold After PPI_CLK
PPI_FS1/2
PPI_DATA
PPI_CLK
PPI_FS1/2
PPI_DATA
PPI_CLK
describe parallel peripheral interface
38,
t
SFSPE
Figure 21 on Page
FRAME SYNC SAMPLED
DATA SAMPLED /
Figure 15. PPI GP Rx Mode with External Frame Sync Timing
Figure 16. PPI GP Tx Mode with External Frame Sync Timing
FRAME SYNC SAMPLED
Rev. A | Page 38 of 72 | August 2010
43, and
t
DATA DRIVEN /
t
SFSPE
t
t
DDTPE
HDTPE
HFSPE
t
SDRPE
t
HFSPE
FRAME SYNC SAMPLED
DATA SAMPLED /
Min
t
2 × t
6.7
1.5
4.1
2
1.7
2.3
SCLK
– 1.5
SCLK
t
1.8 V Nominal
t
PCLKW
PCLKW
– 1.5
t
V
HDRPE
DDMEM
Max
8
8.2
t
t
PCLK
PCLK
Min
t
2 × t
6.7
1.5
3.5
1.6
1.7
1.9
SCLK
– 1.5
SCLK
2.5/3.3 V Nominal
– 1.5
V
DDMEM
Max
8
8
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns