ADUC7021BCPZ62I-RL Analog Devices Inc, ADUC7021BCPZ62I-RL Datasheet - Page 81
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ADUC7021BCPZ62I-RL
Manufacturer Part Number
ADUC7021BCPZ62I-RL
Description
IC,MICROCONTROLLER,16-BIT,ARM7 CPU,CMOS,LLCC,40PIN,PLASTIC
Manufacturer
Analog Devices Inc
Series
MicroConverter® ADuC7xxxr
Datasheet
1.USB-I2CLIN-CONV-Z.pdf
(96 pages)
Specifications of ADUC7021BCPZ62I-RL
Core Processor
ARM7
Core Size
16/32-Bit
Speed
44MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART
Peripherals
PLA, PWM, PSM, Temp Sensor, WDT
Number Of I /o
13
Program Memory Size
62KB (62K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x12b, D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
40-LFCSP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Table 177. T1CON MMR Bit Descriptions
Bit
31:18
17
16:12
11:9
8
7
6
5:4
3:0
Table 178. T1CLRI Register
Name
T1CLRI
T1CLRI is an 8-bit register. Writing any value to this register
clears the Timer1 interrupt.
Value
000
001
010
011
00
01
10
11
0000
0100
1000
1111
Address
0xFFFF032C
Description
Reserved.
Event select bit. Set by user to enable time
capture of an event. Cleared by user to
disable time capture of an event.
Event select range, 0 to 31. These events are
as described in Table 158. All events are
offset by two; that is, Event 2 in Table 158
becomes Event 0 for the purposes of
Timer1.
Clock select.
Core clock (HCLK).
External 32.768 kHz crystal.
P1.0 rising edge triggered.
P0.6 rising edge triggered.
Count up. Set by user for Timer1 to count
up. Cleared by user for Timer1 to count
down by default.
Timer1 enable bit. Set by user to enable
Timer1. Cleared by user to disable Timer1 by
default.
Timer1 mode. Set by user to operate in
periodic mode. Cleared by user to operate in
free-running mode. Default mode.
Format.
Binary.
Reserved.
Hr: min: sec: hundredths (23 hours to 0 hour).
Hr: min: sec: hundredths (255 hours to 0
hour).
Prescale.
Source Clock/1.
Source Clock/16.
Source Clock/256.
Source Clock/32,768.
Default Value
0xFF
Access
W
Rev. C | Page 81 of 96
Table 179. T1CAP Register
Name
T1CAP
T1CAP is a 32-bit register. It holds the value contained in
T1VAL when a particular event occurs. This event must be
selected in T1CON.
Timer2 (Wake-Up Timer)
Timer2 is a 32-bit wake-up timer (count down or count up)
with a programmable prescaler. The source can be the 32 kHz
external crystal, the core clock frequency, or the internal 32 kHz
oscillator. The clock source can be scaled by a factor of 1, 16,
256, or 32,768. The wake-up timer continues to run when the
core clock is disabled.
The counter can be formatted as plain 32-bit value or as
hours: minutes: seconds: hundredths.
Timer2 can be used to start ADC conversions as shown in the
block diagram in Figure 67.
The Timer2 interface consists of four MMRs: T2LD, T2VAL,
T2CON, and T2CLRI.
Table 180. T2LD Register
Name
T2LD
T2LD is a 32-bit register load register.
Table 181. T2VAL Register
Name
T2VAL
T2VAL is a 32-bit read-only register that represents the current
state of the counter.
Table 182. T2CON Register
Name
T2CON
T2CON is the configuration MMR described in Table 183.
ADuC7019/20/21/22/24/25/26/27/28/29
OSCILLATOR
EXTERNAL
INTERNAL
CRYSTAL
HCLK
Address
0xFFFF0330
Address
0xFFFF0340
Address
0xFFFF0344
Address
0xFFFF0348
Figure 67. Timer2 Block Diagram
PRESCALER
OR 32,768
/1, 16, 256
Default Value
0x00000000
Default Value
0x00000000
Default Value
0xFFFFFFFF
Default Value
0x0000
COUNTER
UP/DOWN
TIMER2
VALUE
32-BIT
32-BIT
LOAD
TIMER2 IRQ
Access
R/W
Access
R/W
Access
R
Access
R/W